mosfet basics

```svg ``` **MOSFET** (metal-oxide-semiconductor field-effect transistor) is the fundamental switching device in virtually every integrated circuit manufactured since the 1970s — a voltage-controlled current source where a gate electrode separated from the silicon channel by a thin insulating oxide modulates the conductivity between source and drain terminals. Every logic gate, SRAM cell, analog amplifier, and power converter in modern electronics is built from MOSFETs. The global semiconductor industry fabricates roughly 10²¹ (one sextillion) MOSFETs per year — more than any other manufactured object in human history. **How it works — the field effect.** Applying a positive voltage to the gate (for NMOS) attracts electrons to the silicon surface beneath the oxide, creating a conductive channel that allows current to flow from drain to source. When the gate voltage drops below the threshold voltage $V_t$, the channel disappears and current stops (off-state). This voltage-controlled switch is the basis of all digital logic (0/1) and analog signal processing. **The threshold voltage** determines where the transistor turns on: $$I_{DS} = \mu_n C_{ox} \frac{W}{L} \Bigl[(V_{GS} - V_t)V_{DS} - \frac{V_{DS}^2}{2}\Bigr] \quad \text{(linear region)}$$ $$I_{DS} = \frac{\mu_n C_{ox}}{2} \frac{W}{L} (V_{GS} - V_t)^2 (1 + \lambda V_{DS}) \quad \text{(saturation)}$$ where $\mu_n$ is electron mobility, $C_{ox} = \varepsilon_{ox}/t_{ox}$ is gate-oxide capacitance per unit area, $W/L$ is the width-to-length ratio, and $\lambda$ is the channel-length modulation parameter. These equations (the "square-law" model) capture the first-order behavior; production SPICE models (BSIM-CMG) use 300–600 parameters for nanometer accuracy. **MOSFET evolution — from planar to GAA:** | Era | Structure | Gate control | Node range | Key advantage | |---|---|---|---|---| | Planar bulk | Flat channel, gate on top | 1 side (top only) | >22 nm | Simple, cheap, mature | | SOI (FD-SOI) | Thin Si on insulator | 1 side + back-bias | 22–12 nm | Low variability, body bias knob | | FinFET | Tall narrow fin, gate wraps 3 sides | 3 sides | 22–5 nm | Superior short-channel control | | GAA nanosheet | Stacked horizontal sheets, gate wraps all 4 | 4 sides (all-around) | 3 nm and below | Best electrostatics, width × stacks | Each generation improves **electrostatic control** — the ability of the gate to turn the channel on/off without leakage. Better control means the transistor can be shorter (faster) without leaking when off. **Key MOSFET parameters for chip designers:** | Parameter | Symbol | What it means | Typical at 5 nm | |---|---|---|---| | Threshold voltage | $V_t$ | Gate voltage where channel turns on | 0.2–0.4 V | | Drive current | $I_{on}$ | Current when fully on (VGS=VDS=VDD) | 1–2 mA/µm | | Off-state leakage | $I_{off}$ | Current when gate is at 0V | 1–100 nA/µm | | Subthreshold swing | SS | mV of gate needed per decade of current | 62–70 mV/dec | | DIBL | — | Drain-induced barrier lowering | 20–40 mV/V | | Transconductance | $g_m$ | dI/dV sensitivity | 1–3 mS/µm | | Transit frequency | $f_T$ | Speed limit for analog | 300–500 GHz | | Gate capacitance | $C_{gg}$ | Input capacitance (sets CV²f power) | ~0.5 fF/µm | **The on/off ratio** ($I_{on}/I_{off}$) is the single most important figure of merit — it determines how fast the chip can switch (high $I_{on}$) while staying within its power budget (low $I_{off}$). Modern FinFETs achieve $10^6$–$10^7$ on/off ratio; the CFS Transistor Simulator at /transistor models this directly. **Short-channel effects — why scaling is hard.** As the gate length shrinks below ~50 nm, the drain's electric field begins to compete with the gate's control over the channel. This causes: (1) **DIBL** — drain voltage lowers the barrier, increasing off-current; (2) **Vt roll-off** — threshold voltage decreases with gate length; (3) **velocity saturation** — carriers reach maximum speed regardless of further field increase; (4) **gate-induced drain leakage (GIDL)** — band-to-band tunneling at the drain edge. Each generation of MOSFET architecture (planar → FinFET → GAA) is designed to suppress these effects by giving the gate more physical control over the channel. **MOSFET in the CFS ecosystem.** The CFS Transistor Simulator at /transistor solves the electrostatics and I-V curves for FinFET and GAA devices. The gate-all-around keyword covers the latest architecture. The standard cell keyword shows how MOSFETs are assembled into logic. The ion implantation keyword covers how source/drain doping is formed. Every simulation on the platform — from etch profiles to thermal hotspots — ultimately exists to make better MOSFETs.