nanosheet channel
**Nanosheet Channel Formation** is the **process of creating suspended horizontal silicon sheets that form the transistor channel in Gate-All-Around (GAA) transistors** — enabling the gate to wrap fully around the channel for superior electrostatic control at sub-3nm.
**Why Nanosheets?**
- FinFET limit: At < 3nm gate length, fin width must be < 6nm → manufacturing variability dominates.
- GAAFET nanosheet: Gate wraps all four sides → better SCE control, allows wider channel for more current.
**Nanosheet Stack Formation**
1. **Superlattice Growth**: Alternating SiGe and Si layers grown epitaxially:
```
Si (nanosheet channel, 5-8nm thick)
SiGe (sacrificial layer, 8-10nm thick)
Si (channel)
SiGe (sacrificial)
Si (channel) [3-5 pairs typical]
```
2. **Fin Patterning**: SADP/SAQP to pattern fin pitch (same as FinFET).
3. **Fin Etch**: Etch through entire superlattice to form nanosheet "stack fin".
**Dummy Gate Formation (Same as Gate-Last Flow)**
1. Gate oxide + poly gate deposited over stack fin.
2. Poly gate patterned, spacers formed.
3. S/D recess, SiGe S/D epi, PMD deposit, CMP.
**Inner Spacer Formation**
1. SiGe layers laterally recessed through dummy gate-adjacent region: H2O2 or HCl.
2. Inner spacer material (SiN or SiCO) deposited by ALD — fills recess.
3. Etch back inner spacer to leave only the lateral recess filled.
4. Inner spacers isolate SiGe sacrificial from future metal gate.
**Channel Release (Nanosheet Release)**
1. Remove dummy poly gate (replacement gate flow).
2. Selective SiGe etch inside gate cavity: H2O2 or HCl removes SiGe, not Si.
3. SiGe:Si selectivity > 100:1 — leaves free-standing Si nanosheets between inner spacers.
4. Nanosheets now suspended — gate wraps all four sides.
**Gate Fill**
- ALD HfO2 conformal around all nanosheets.
- ALD TiN work function metal wraps each sheet.
- WN or W fill metal completes gate stack.
Nanosheet GAA transistor fabrication is **the most complex process sequence in the history of CMOS** — requiring precise SiGe/Si superlattice growth, inner spacer formation, and selective channel release to create floating silicon bridges at nanometer scale.