Nanowire Transistor Process

# Nanowire Transistor Process: Channel Formation, 1D Transport & Vertical Scaling

In advanced nanoelectronics, the Nanowire Field-Effect Transistor (NW-FET) represents the ultimate electrostatic limit of Gate-All-Around (GAA) channel architecture. While wide rectangular nanosheets (Multi-Bridge Channel FETs, or MBCFETs) were commercialized at the $3\,\text{nm}$ and $2\,\text{nm}$ nodes to maximize drive current per standard-cell footprint, cylindrical and vertically oriented silicon/germanium nanowires ($d_{nw} \approx 4\text{ to }8\,\text{nm}$) achieve the highest degree of electrostatic gate control achievable in solid-state physics.

By wrapping the high-k dielectric and metal gate electrode around the full $360^\circ$ perimeter of the semiconductor channel, NW-FETs suppress short-channel effects (SCE), eliminate drain-induced barrier lowering (DIBL), and approach the thermodynamic subthreshold swing limit ($SS \approx 62\text{--}65\,\text{mV/decade}$ at $300\,\text{K}$). Furthermore, when wire diameters scale below the de Broglie wavelength of electrons ($\lambda_{dB} \approx 7\text{ to }10\,\text{nm}$ in silicon), carriers transition into a one-dimensional (1D) quantum confinement regime, where discrete subbands and reduced inter-subband scattering enable quasi-ballistic transport with conductance approaching the Landauer quantum limit ($G_0 = 2e^2/h$).

Nanowire Channel Formation & 360° Radial Electrostatics selective SiGe release, corner rounding anneal, and radial equipotential field contours NANOWIRE FABRICATION SEQUENCE 1. Epitaxial Superlattice Fin Etching: Epitaxial growth of alternating Si / Si₀.₇Ge₀.₃ layers. Anisotropic RIE vertical fin patterning (AR > 5:1). 2. Selective Lateral Isotropic SiGe Etch: Gas-phase vapor HF/O₃ or CF₄/O₂ chemical dry etch. Etch selectivity > 150:1 removes SiGe, releasing Si wires. 3. Hydrogen Anneal & Corner Rounding: High-temperature H₂ bake (750°C–850°C) or thermal ox. Silicon surface atom migration rounds square wire corners. 4. ALD High-κ & Metal Gate (HKMG): Atomic Layer Deposition of interfacial SiO₂ + HfO₂. 360° TiN / W work-function metal fill wraps channel. Key Manufacturing Tolerances: • Wire Diameter: d_nw = 5.0 ± 0.4 nm (3σ control) • Vertical Wire-to-Wire Pitch: P_vert = 12–15 nm • Surface Roughness: RMS < 0.15 nm to preserve mobility • Inner Spacer Width: L_sp = 5–7 nm (lowers C_ov) • Stacking: 3 to 5 vertically stacked horizontal wires per fin footprint to recover drive current I_on. CORNER EFFECT VS. CYLINDRICAL WRAP A. Unrounded Square Wire (Corner Field Crowding): Si Wire • Electric Field Singularity: Sharp 90° corners induce electric field crowding: E_corner ≫ E_flat • Early gate dielectric breakdown • Corner parasitic leakage channels B. Rounded Cylindrical Nanowire (Uniform 360°): Si Core • Ideal Radial Field Distribution: E(r) = Q / (2πε · r) is radially uniform • Zero corner crowding / uniform oxide • Natural Scaling Length λ ≈ 2.1 nm • Subthreshold Swing SS → 62 mV/dec Cylindrical Screening Length Formulation: λ_cyl = √[ (ε_ch / 4ε_ox) · d_nw² · ln(1 + 2t_ox / d_nw) ] • For d_nw = 5 nm, t_ox = 1.2 nm: λ_cyl ≈ 2.0 nm • Scaling Rule: L_gate ≥ 3 · λ_cyl ≈ 6.0 nm without DIBL

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## 1. Electrostatic Scaling & Screening Length Physics

The short-channel immunity of any field-effect transistor is parameterized by its natural electrostatic screening length $\lambda$. When the physical gate length $L_g$ exceeds $3\lambda$ ($L_g \ge 3\lambda$), the central channel potential is determined exclusively by the gate voltage $V_g$, and electrostatic coupling from the drain is screened out ($DIBL < 20\,\text{mV/V}$).

Horizontal vs. Vertical Nanowires & 1D Quantum Transport structural comparison, cell-area scaling, and 1D subband energy quantization HORIZONTAL VS. VERTICAL ARCHITECTURES Horizontal GAA Nanowire (HNWFET): Source Drain Gate (L_g) Lateral Current Flow | Area constrained by CPP Vertical Nanowire FET (VNWFET): Top Drain (D) Gate L_g Bottom Source (S) Decouples L_g from Cell Footprint: Extends Moore's Law < 40 nm CPP 1D QUANTUM TRANSPORT & SUBBANDS k_z Energy E Subband 1 (E₁) Subband 2 (E₂) Subband 3 (E₃) ΔE > 100 meV 1D Subband Quantization (d_nw < 7 nm): E_n = [ ℏ² · π² / (2 · m*) ] · [ (n_x / d_x)² + (n_y / d_y)² ] 1D Density of States (Van Hove Singularity): g_1D(E) = (1 / πℏ) · √[ m* / 2(E - E_n) ] ∝ (E - E_n)^(-1/2) Ballistic Landauer Quantum Conductance: G_ballistic = M · ( 2e² / h ) ≈ M · 77.48 μS per subband • Large subband spacing (ΔE ≫ k_B T) suppresses phonon inter-subband scattering, boosting carrier injection velocity.

### 1.1 Natural Screening Length: Architecture Comparison
The natural screening length represents the spatial decay constant of electrostatic disturbances along the channel. Comparing classic double-gate (DG) FinFETs with cylindrical GAA nanowires:

  • Double-Gate / Tri-Gate FinFET:
$$\lambda_{DG} = \sqrt{\frac{\epsilon_{ch}}{2\epsilon_{ox}} t_{si} t_{ox} \left( 1 + \frac{\epsilon_{ox} t_{si}}{4 \epsilon_{ch} t_{ox}} \right)}$$
  • Cylindrical Gate-All-Around Nanowire:
$$\lambda_{cyl} = \sqrt{\frac{\epsilon_{ch}}{4\epsilon_{ox}} d_{nw}^2 \ln\left( 1 + \frac{2 t_{ox}}{d_{nw}} \right)}$$

Where:
- $\epsilon_{ch} \approx 11.7\,\epsilon_0$ (permittivity of silicon).
- $\epsilon_{ox} \approx 3.9\,\epsilon_0$ (effective interfacial $\text{SiO}_2$ equivalent oxide thickness, $\text{EOT}$).
- $d_{nw}$ is the nanowire diameter ($5.0\,\text{nm}$).
- $t_{ox}$ is the physical gate dielectric thickness ($1.2\,\text{nm}$).

Evaluating for $d_{nw} = 5.0\,\text{nm}$:

$$\lambda_{cyl} = \sqrt{\frac{11.7}{4(3.9)} (5.0 \times 10^{-9})^2 \ln\left( 1 + \frac{2(1.2)}{5.0} \right)} \approx \mathbf{2.02\,\text{nm}}$$

Because $\lambda_{cyl} \approx 2.0\,\text{nm}$, a cylindrical nanowire maintains ideal long-channel behavior down to physical gate lengths of:

$$L_{g,min} \ge 3 \cdot \lambda_{cyl} \approx 6.0\text{ to }6.5\,\text{nm}$$

In contrast, a standard FinFET with fin width $W_{fin} = 6\,\text{nm}$ exhibits $\lambda_{fin} \approx 4.5\,\text{nm}$, limiting its physical gate length scaling to $L_g \ge 14\,\text{nm}$.

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## 2. 1D Quantum Transport & Landauer Ballistic Conductance

When the wire diameter is reduced below the thermal de Broglie wavelength ($\lambda_{dB} \approx 7\text{ to }10\,\text{nm}$ for silicon electrons at $300\,\text{K}$), transverse momentum is completely quantized into discrete energy states:

$$E_{n_x, n_y}(k_z) = E_C + \frac{\hbar^2 \pi^2}{2 m^*}\left( \frac{n_x^2}{d_x^2} + \frac{n_y^2}{d_y^2} \right) + \frac{\hbar^2 k_z^2}{2 m_z^*}$$

Where:
- $n_x, n_y = 1, 2, 3, \dots$ are transverse quantum numbers.
- $m^*$ is the transverse electron effective mass.
- $k_z$ is the unconstrained continuous wavevector along the transport direction.

+----------------------------------------------------------------------------------------------------+
|                                    NANOWIRE QUANTUM TRANSPORT PROPERTIES                           |
+--------------------+--------------------+--------------------+--------------------+----------------+
| PARAMETER          | BULK / PLANAR SI   | FINFET (3D / 2D)   | NANOSHEET (MBCFET) | NANOWIRE (1D)  |
+--------------------+--------------------+--------------------+--------------------+----------------+
| Transverse DOFs    | 0 Quantized (3D)   | 1 Quantized (2D)   | 1 Quantized (2D)   | 2 Quantized(1D)|
+--------------------+--------------------+--------------------+--------------------+----------------+
| Density of States  | g(E) ∝ √E          | g(E) = Stepwise    | g(E) = Stepwise    | g(E) ∝ 1/√E    |
|                    | (Continuous)       | (2D subbands)      | (2D subbands)      | (Van Hove Sing)|
+--------------------+--------------------+--------------------+--------------------+----------------+
| Phonon Scattering  | 3D Acoustic / Opt  | Surface Roughness  | Surface Roughness  | Suppressed     |
| Rates              | (Standard)         | & Phonon limited   | limited (broad)    | (Large ΔE)     |
+--------------------+--------------------+--------------------+--------------------+----------------+
| Ballistic Limit    | ~ 15% to 25%       | ~ 40% to 55%       | ~ 50% to 65%       | > 80% to 90%   |
| Ratio (I_on/I_bal) | (Drift-diffusion)  | (Quasi-ballistic)  | (Quasi-ballistic)  | (Near ballistic|
+--------------------+--------------------+--------------------+--------------------+----------------+

### 2.1 Landauer Conductance Quantum
In the ballistic limit where channel length $L_g$ is comparable to or shorter than the electron mean free path ($\lambda_{mfp} \approx 10\text{ to }15\,\text{nm}$ in low-field silicon), current is not governed by drift-diffusion mobility ($\mu$), but by the transmission probability $\mathcal{T}(E)$ and the number of populated subbands $M(E)$:

$$I_D = \frac{2e}{h} \sum_{i=1}^M \int_{E_i}^\infty \mathcal{T}_i(E) \left[ f_{FD}(E - E_{FS}) - f_{FD}(E - E_{FD}) \right] \, dE$$

At low drain bias, this yields the fundamental Landauer quantum conductance per populated 1D subband:

$$G_0 = \frac{2e^2}{h} \approx 77.48\,\mu\text{S} \implies R_{contact,min} = \frac{1}{G_0} \approx 12.9\,\text{k}\Omega$$

Because the energy subband separation $\Delta E = E_2 - E_1 > 100\,\text{meV}$ exceeds the room-temperature thermal energy ($k_B T \approx 25.9\,\text{meV}$), electrons remain restricted to the lowest subband ($n_x=1, n_y=1$). This eliminates inter-subband scattering, boosting carrier injection velocity to $v_{inj} > 1.2 \times 10^7\,\text{cm/s}$ (compared to $v_{sat} \approx 8 \times 10^6\,\text{cm/s}$ in planar silicon).

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## 3. Horizontal vs. Vertical Nanowires (VNWFET)

While horizontal nanowires (HNWFETs) share the same lateral self-aligned layout as nanosheets, they face an intrinsic footprint limitation: the contacted poly pitch (CPP) establishes the lateral boundary ($CPP = L_g + 2 L_{sp} + L_{cont} \approx 40\text{ to }45\,\text{nm}$).

+----------------------------------------------------------------------------------------------------+
|                                    HNWFET VS. VNWFET ARCHITECTURAL MATRIX                          |
+--------------------+--------------------+--------------------+-------------------------------------+
| ATTRIBUTE          | HORIZONTAL NW (HNWFET)                  | VERTICAL NW (VNWFET)                |
+--------------------+--------------------+--------------------+-------------------------------------+
| Transport Vector   | Lateral (along substrate plane)         | Vertical (perpendicular to wafer)   |
+--------------------+--------------------+--------------------+-------------------------------------+
| Cell Footprint     | Constrained by CPP and fin width        | Decoupled from Gate Length (Lg);    |
| Scaling            | (CPP ≥ 42 nm scaling limit)             | cell pitch dictated by wire pitch   |
+--------------------+--------------------+--------------------+-------------------------------------+
| Gate Length Control| Lithography & Spacer defined (EUV limit)| Film Thickness defined (ALD gate    |
|                    | prone to line-edge roughness (LER)      | deposition provides atomic control) |
+--------------------+--------------------+--------------------+-------------------------------------+
| Drive Current /    | Low per wire; requires 3–5 vertically   | High per area; dense hexagonal wire |
| Footprint Area     | stacked wires to equal nanosheet I_on   | arrays achieve maximum packaging    |
+--------------------+--------------------+--------------------+-------------------------------------+
| Parasitic C_gd/C_gs| High overlap capacitance across spacers | Asymmetric: top spacer can be thick |
| Optimization       | (symmetric front/back gate spacers)     | while bottom contact is buried      |
+--------------------+--------------------+--------------------+-------------------------------------+

In Vertical Nanowire FETs (VNWFETs), the source is located at the base of the silicon pillar, the gate wraps around the pillar body, and the drain is placed on top. This geometry completely decouples gate length $L_g$ and spacer thickness from horizontal cell layout, providing a direct architectural roadmap for standard-cell scaling beyond the sub-$1\,\text{nm}$ node.

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