Vertical Transistor Structures

# Vertical Transistor Structures: VTFET Architecture, Nanofabrication & Parasitic Scaling

As conventional lateral field-effect transistors—including FinFETs and lateral Gate-All-Around (GAA) nanosheets—scale toward the sub-$1\,\text{nm}$ regime, they confront a geometric scaling wall imposed by the Contacted Poly Pitch (CPP). In any lateral transistor, the source, gate, and drain sit side-by-side along the wafer plane, enforcing a fundamental pitch constraint:

$$CPP_{lateral} = L_g + 2 L_{spacer} + L_{contact} \ge 42\text{ to }45\,\text{nm}$$

Scaling $CPP$ in lateral architectures requires aggressively shrinking the physical gate length ($L_g < 12\,\text{nm}$), exacerbating Drain-Induced Barrier Lowering (DIBL), gate leakage, and contact resistance.

Vertical-Transport Field-Effect Transistors (VTFET / V-GAA) break this paradigm by rotating the transport current vector $90^\circ$ perpendicular to the wafer surface. In a vertical architecture, the source is located at the base of a vertical silicon/germanium nanopillar, the gate wraps $360^\circ$ around the vertical pillar sidewalls, and the drain terminates at the pillar apex. This orientation completely decouples physical gate length ($L_g$), spacer thicknesses ($L_{spacer}$), and contact dimensions from the lateral cell footprint, slashing the effective device pitch to $20\text{ to }24\,\text{nm}$ and shrinking 6T SRAM bitcells by $> 45\%$.

Lateral GAA Nanosheet vs. Vertical-Transport FET (VTFET) geometric footprint comparison, current transport vectors, and pitch scaling limits 1. LATERAL GAA (CPP-CONSTRAINED) Source Gate (L_g) Drain Lateral Current Vector → CPP = L_g + 2 L_sp + L_cont ≥ 45 nm Lateral Scaling Limitations: • L_g is directly constrained by lateral footprint. • Shrinking CPP forces L_g < 12 nm ⟹ severe DIBL, threshold voltage roll-off, and gate oxide tunneling. • Thinning gate spacers (< 4 nm) causes massive parasitic gate-to-contact capacitance (C_ov + C_fringe). Area & Contact Density Ceiling: • Standard Cell Height: 5T to 6T tracks (~120–140 nm) • 6T SRAM Bitcell Area: ~0.021 μm² at 2 nm node • High interconnect congestion at Middle-of-Line (MOL) 2. VERTICAL-TRANSPORT FET (VTFET) Top Drain Top Spacer (t_tsp) Pillar Gate Gate Thick Bottom Spacer (t_bsp ≈ 12 nm) Bottom Source (Substrate / Backside) Vertical I_D ↑ CPP_vertical ≈ 20 to 24 nm Vertical Architecture Advantages: • L_g is defined vertically by deposition (not litho). • Relaxed L_g (18–22 nm) yields near-zero DIBL (< 30 mV/V) without increasing the transistor cell footprint! • Bottom spacer can be made thick (10–15 nm), cutting parasitic C_gs overlap capacitance by > 50%. Density & Memory Scaling Impact: • Lateral Contacted Pitch: Scaled down to 20–24 nm • 6T SRAM Bitcell Area: < 0.012 μm² (> 45% scaling) • Direct integration with Backside Power Delivery Networks

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## 1. Lateral vs. Vertical Architecture Comparison

The physical transition from lateral transport to vertical transport eliminates the geometry trade-offs that constrain lateral nanosheet roadmap scaling:

+----------------------------------------------------------------------------------------------------+
|                                LATERAL GAA VS. VERTICAL FET ARCHITECTURAL COMPARISON               |
+--------------------+--------------------+--------------------+-------------------------------------+
| DESIGN PARAMETER   | LATERAL NANOSHEET (MBCFET / GAA)        | VERTICAL TRANSPORT FET (VTFET)      |
+--------------------+--------------------+--------------------+-------------------------------------+
| Transport Vector   | Lateral (Parallel to wafer plane)       | Vertical (Perpendicular to wafer)   |
+--------------------+--------------------+--------------------+-------------------------------------+
| Lateral Pitch Limit| CPP = L_g + 2 L_sp + L_cont             | Metal Pitch / Pillar Diameter       |
|                    | Minimum CPP ≈ 42 to 45 nm               | Minimum Pitch ≈ 20 to 24 nm         |
+--------------------+--------------------+--------------------+-------------------------------------+
| Gate Length (L_g)  | Defined by EUV lithography & etching;   | Defined by ALD thin-film deposition |
| Definition         | scaled down to ~12 nm (severe DIBL)     | relaxed to 18–22 nm (near-zero DIBL)|
+--------------------+--------------------+--------------------+-------------------------------------+
| Spacer Engineering | Symmetric thin spacers (< 4 nm)         | Asymmetric: bottom spacer 12–15 nm; |
|                    | required to fit within CPP              | slashes gate-drain overlap C_gd     |
+--------------------+--------------------+--------------------+-------------------------------------+
| Drive Current /    | W_eff = 2 · N_sheets · (W_ns + T_ns)    | W_eff = π · d_pillar (cylindrical)  |
| Effective Width    | High current per fin; wide footprint    | High current density per unit area  |
+--------------------+--------------------+--------------------+-------------------------------------+
| 6T SRAM Bitcell    | ~0.021 μm² (at 2 nm lateral node)       | < 0.012 μm² (> 45% area scaling)    |
| Footprint          | Severe wire routing congestion          | Pillar array shared routing tracks  |
+--------------------+--------------------+--------------------+-------------------------------------+
VTFET Nanofabrication Sequence & Parasitic Capacitance Breakdown high-aspect-ratio pillar etching, asymmetric spacer recess, and parasitic RC scaling VTFET NANOFABRICATION SEQUENCE Step 1: High-AR Pillar Etch (Cryo-RIE) • Anisotropic etching of single-crystal Si (AR > 10:1, θ ≈ 89.8°) • Hardmask: SiN / TiN mandrel defines diameter d_pillar ≈ 8–10 nm • In situ bottom source epitaxy pre-implanted into base substrate Step 2: Bottom Spacer Formation & Recess • Directional gas-cluster ion deposition of low-k dielectric (SiBCN) • Controlled anisotropic dry etch-back sets thickness t_bsp = 12 nm • Completely isolates bottom source from vertical gate electrode Step 3: 360° HKMG Conformality & Gate Recess • Atomic Layer Deposition (ALD) of HfO₂/TiN wraps 360° around pillar • Chemical mechanical planarization (CMP) + selective timed etch-back • Defines physical gate length vertically: L_g = 18–22 nm Step 4: Top Spacer & Top Drain Epitaxy • Conformal ALD top dielectric spacer encapsulation (t_tsp ≈ 5 nm) • Selective epitaxy of highly-doped Si:P / SiGe:B top drain contact • Middle-of-Line (MOL) contact landing with zero lithographic pitch error PARASITIC CAPACITANCE SCALING Total Transistor Capacitance Network: C_total = C_gate + C_ov,top + C_ov,bottom + C_fringe Asymmetric Spacer Advantage: • C_ov,bottom = (ε_spacer · ε₀ · A_bottom) / t_bsp • Increasing t_bsp from 4 nm (lateral) to 12 nm (VTFET) reduces bottom overlap capacitance by > 65%! • Net transistor parasitic capacitance drops by 32%. Intrinsic Propagation Delay & Power Scaling: τ_delay = ( C_total · V_dd ) / I_on Electrostatic Natural Scaling Length (λ_cyl): • λ = √[ (2 ε_si · d² · ln(1 + 2 t_ox/d) + ε_ox · d²) / (8 ε_ox) ] • For d_pillar = 8 nm, EOT = 0.8 nm ⟹ λ ≈ 2.4 nm • With relaxed L_g = 18 nm: L_g / λ ≈ 7.5 ≫ 5.0 (Near-ideal!) Key Performance Figures of Merit: • DIBL: < 30 mV/V (vs. > 75 mV/V in scaled lateral GAA) • Subthreshold Swing (SS): ~64 mV/dec at room temp • Iso-Performance Power: Cuts dynamic switching power by ~50%

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## 2. Nanofabrication Sequence: Decoupling $L_g$ and Spacers

The manufacturing process of vertical-transport transistors inverts the conventional planar/fin FEOL hierarchy:

### 2.1 Anisotropic High-Aspect-Ratio Pillar Etch
The vertical channel is defined by dry etching single-crystal silicon or silicon-germanium epilayers. A dielectric hardmask stack (silicon nitride $\text{Si}_3\text{N}_4$ atop titanium nitride $\text{TiN}$) is patterned using high-NA EUV lithography.

Etching is executed in an inductively coupled plasma (ICP) reactor utilizing cryogenic fluorine chemistry ($\text{SF}_6 / \text{O}_2$ at $-100^\circ\text{C}$):
- Pillar diameter: $d_{pillar} \approx 6\text{ to }10\,\text{nm}$.
- Pillar height: $h_{pillar} \approx 60\text{ to }80\,\text{nm}$.
- Aspect ratio: $AR > 8:1\text{ to }10:1$ with vertical sidewall angle $\theta \approx 89.8^\circ \pm 0.2^\circ$.

### 2.2 Directional Bottom Spacer Deposition
In lateral architectures, spacer thickness cannot exceed $3.5\text{ to }4.5\,\text{nm}$ without encroaching upon the contacted poly pitch. In VTFET, the bottom spacer sits on the horizontal wafer surface.

A low-k dielectric film (silicon boron carbon nitride, $\text{SiBCN}$, $\kappa \approx 4.2$) is deposited using directional gas-cluster ion-beam (GCIB) deposition or high-density plasma CVD (HDP-CVD). An anisotropic fluorine-based etch-back removes dielectric from the pillar vertical sidewalls while preserving a thick, robust bottom spacer:

$$t_{bsp} \approx \mathbf{10\text{ to }15\,\text{nm}}$$

This thick dielectric barrier slashes the parasitic gate-to-source overlap capacitance:

$$C_{ov,bottom} = \frac{\epsilon_{spacer} \epsilon_0 A_{contact}}{t_{bsp}}$$

Increasing $t_{bsp}$ from $4\,\text{nm}$ to $12\,\text{nm}$ reduces bottom parasitic capacitance by $> 65\%$.

### 2.3 $360^\circ$ High-k Metal Gate (HKMG) Wrap & Vertical Recess
Atomic layer deposition (ALD) lines the exposed vertical channel sidewalls with an interfacial silicon oxide ($\text{SiO}_x \approx 0.5\,\text{nm}$), followed by high-k hafnium dioxide ($\text{HfO}_2 \approx 1.5\,\text{nm}$) and atomic-layer-deposited work-function metal bilayers (TiN, TaN, TiAlC).

A blanket sacrificial filling material (e.g., spin-on carbon, SOC) is coated, planarized by chemical-mechanical planarization (CMP), and selectively recessed using a timed reactive ion etch. The metal gate layer is subsequently etched back to the recess plane. This vertical recess height precisely establishes the physical gate length:

$$L_g \approx \mathbf{18\text{ to }22\,\text{nm}}$$

Because $L_g$ is determined by an etch-back depth along the Z-axis, it can be engineered generously without expanding the lateral standard cell footprint.

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## 3. Electrostatics & Parasitic Capacitance Scaling

The cylindrical gate-all-around boundary condition of the vertical pillar maximizes electrostatic gate control.

### 3.1 Electrostatic Natural Scaling Length ($\lambda_{cyl}$)
For a cylindrical channel of diameter $d_{pillar}$ wrapped by gate dielectric of thickness $t_{ox}$, the electrostatic natural scaling length $\lambda_{cyl}$ derived from Poisson's equation is:

$$\lambda_{cyl} = \sqrt{\frac{2 \epsilon_{ch} d_{pillar}^2 \ln\left(1 + \frac{2 t_{ox}}{d_{pillar}}\right) + \epsilon_{ox} d_{pillar}^2}{8 \epsilon_{ox}}}$$

Evaluating for a silicon pillar with $d_{pillar} = 8\,\text{nm}$, $\epsilon_{ch} = 11.7$, $\epsilon_{ox} = 22$ ($\text{HfO}_2$), and physical $t_{ox} = 1.8\,\text{nm}$ ($EOT \approx 0.8\,\text{nm}$):

$$\lambda_{cyl} \approx \mathbf{2.42\,\text{nm}}$$

To maintain robust short-channel immunity and suppress DIBL below $35\,\text{mV/V}$, the ratio of gate length to scaling length must satisfy:

$$\frac{L_g}{\lambda_{cyl}} \ge 5.0$$

In lateral nanosheets, forcing $CPP \le 45\,\text{nm}$ limits $L_g \approx 12\,\text{nm}$, yielding $L_g / \lambda \approx 4.0\text{ to }4.5$ and degrading subthreshold slope. In VTFET, the relaxed $L_g = 18\,\text{nm}$ yields:

$$\frac{L_g}{\lambda_{cyl}} = \frac{18\,\text{nm}}{2.42\,\text{nm}} \approx \mathbf{7.44} \gg 5.0$$

This complete short-channel suppression enables VTFETs to operate at room temperature with near-ideal subthreshold swings ($SS \approx 64\,\text{mV/dec}$), allowing supply voltage scaling from $V_{dd} = 0.75\,\text{V}$ down to $0.55\,\text{V}$.

### 3.2 Dynamic Power & Switching Speed
The intrinsic device propagation delay is governed by total capacitance and drive current:

$$\tau = \frac{C_{total} V_{dd}}{I_{on}} = \frac{(C_{gate} + C_{ov,top} + C_{ov,bot} + C_{fringe}) V_{dd}}{I_{on}}$$

Dynamic switching power dissipation in logic gates scales quadratically with supply voltage:

$$P_{dynamic} = \alpha \cdot C_{total} \cdot V_{dd}^2 \cdot f$$

By combining a $30\%\text{ to }35\%$ reduction in total parasitic capacitance (via thick asymmetric bottom spacers) with a $25\%$ reduction in operating voltage $V_{dd}$ (enabled by $L_g / \lambda > 7$), VTFET architectures achieve up to a $50\%$ reduction in dynamic power dissipation at iso-frequency compared to leading-edge lateral nanosheet devices.

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