negative bias temperature instability (nbti)

Negative bias temperature instability (NBTI) is a reliability degradation mechanism in PMOS transistors where negative gate bias at elevated temperature causes threshold voltage (Vt) to shift, reducing drive current over the device lifetime. Mechanism: (1) Reaction phase—holes at Si/SiO₂ interface break Si-H bonds, creating interface traps (Nit) that shift Vt; (2) Diffusion phase—released hydrogen diffuses away from interface; (3) Recovery—partial Vt recovery when stress removed (hydrogen back-diffusion). NBTI in PMOS: gate at VDD (negative Vgs in PMOS) creates inversion layer with holes at interface—stress condition. Key dependencies: (1) Temperature—Arrhenius acceleration (Ea ≈ 0.1-0.15 eV); (2) Voltage—power-law dependence on |Vgs|; (3) Time—power-law degradation ΔVt ∝ tⁿ (n ≈ 0.15-0.25). PBTI (positive bias temperature instability): analogous mechanism in NMOS with high-κ dielectrics—electron trapping in HfO₂ bulk traps. NBTI impact: (1) Vt increase reduces PMOS drive current; (2) Circuit slowdown over lifetime; (3) SRAM stability degradation; (4) Timing margin erosion. Measurement: fast pulsed I-V (avoid recovery during measurement), on-chip monitors. AC vs. DC: AC NBTI less severe due to partial recovery during off phase—duty cycle dependent. Mitigation: (1) Process—improve Si/SiO₂ interface quality, optimize high-κ deposition, nitrogen passivation; (2) Design—NBTI-aware timing margins (age-aware STA, guardband), voltage derating. Advanced nodes: NBTI remains relevant for FinFET and GAA, with additional complexity from multi-interface channel structures. One of the key reliability mechanisms that determines guardband sizing and effective transistor performance over product lifetime.