semiconductor aging wearout

**Semiconductor Aging and Wearout Mechanisms** are the **fundamental physical degradation processes — Hot Carrier Injection (HCI), Bias Temperature Instability (BTI), Electromigration (EM), and Time-Dependent Dielectric Breakdown (TDDB) — that progressively damage transistors and interconnects during operation, ultimately causing parametric drift, speed loss, and functional failure over the chip's rated lifetime**. **Why Aging Matters More at Advanced Nodes** Smaller transistors operate at higher electric fields relative to their dimensions. A 30 Angstrom gate oxide at 0.7V experiences the same field as a 100 Angstrom oxide at 2.3V. Higher fields accelerate every degradation mechanism. Simultaneously, design margins shrink — a 5% Vth shift that was harmless at 28nm can cause timing failure at 3nm. **The Four Major Mechanisms** - **Bias Temperature Instability (NBTI/PBTI)**: Sustained gate bias at elevated temperature creates interface traps and oxide charges that shift the threshold voltage. NBTI affects PMOS (negative gate bias); PBTI affects NMOS with high-k dielectrics. BTI partially recovers when bias is removed, complicating measurement and modeling. - **Hot Carrier Injection (HCI)**: High-energy carriers near the drain are injected into the gate oxide, creating permanent interface traps. HCI degrades drain current and increases threshold voltage. Worst-case stress occurs at maximum drain voltage with moderate gate overdrive. - **Electromigration (EM)**: High current density in metal interconnects (especially copper) causes momentum transfer from electrons to metal atoms, physically displacing atoms until voids (opens) or hillocks (shorts) form. EM is the dominant wearout mechanism for narrow BEOL wires at advanced nodes. - **Time-Dependent Dielectric Breakdown (TDDB)**: Sustained voltage stress across the gate oxide gradually creates defects until a conductive percolation path forms, catastrophically shorting the gate to the channel. TDDB is projected to chip lifetime using voltage-accelerated stress tests. **Reliability Qualification** - **HTOL (High Temperature Operating Life)**: Chips are operated at 125°C with accelerated voltage for 1000 hours. The measured parametric drift is extrapolated to the rated lifetime (typically 10 years at nominal conditions) using Arrhenius and power-law models. - **Guardbanding**: Design tools apply aging-aware timing analysis — STA runs with degraded transistor models that reflect end-of-life Vth shifts, ensuring the chip meets timing specifications even after 10 years of continuous operation. Semiconductor Aging Mechanisms are **the slow, invisible physics that define every chip's expiration date** — and the reliability engineering that guardbands against them is what separates a chip that lasts a decade from one that fails in the field.