on chip bus interconnect

**On-Chip Interconnect and NoC Architecture** is the **communication fabric that connects all IP blocks (CPU cores, GPU, memory controllers, I/O peripherals, accelerators) within an SoC — where the interconnect topology, protocol, bandwidth, and latency jointly determine system performance as directly as the processing elements themselves, making interconnect design one of the most critical aspects of modern SoC architecture**. **Evolution from Bus to Network** - **Shared Bus (Legacy)**: A single set of address/data/control wires shared by all masters and slaves. Only one transaction at a time. Adequate for simple microcontrollers but bandwidth-limited for multi-core SoCs. - **Crossbar**: Full N×M switch connecting N masters to M slaves simultaneously. High bandwidth but area scales as O(N×M) — impractical beyond ~16 ports. - **Network-on-Chip (NoC)**: A packet-switched micro-network with routers at each IP block. Data is packetized, routed through multiple hops, and delivered. Scales to hundreds of endpoints with predictable latency and bandwidth. Used in all high-performance SoCs (Arm CMN, NVIDIA NVLink on-chip, Synopsys/Arteris NoC IP). **Standard Protocols** - **AMBA AXI (Advanced eXtensible Interface)**: The dominant on-chip protocol. AXI4 supports burst transfers up to 256 beats, separate read/write channels, outstanding transactions, and out-of-order completion. AXI4-Lite is a simplified version for control registers. AXI4-Stream is for unidirectional streaming data (DMA, video pipeline). - **AMBA ACE/CHI**: Cache-coherent extensions of AXI. ACE (AXI Coherency Extensions) adds snoop/response channels for hardware cache coherence between CPU clusters. CHI (Coherent Hub Interface) is the next-generation protocol for Arm's mesh interconnects with distributed snoop filtering. - **TileLink**: RISC-V ecosystem cache-coherent interconnect protocol, with TL-UL (uncached), TL-UH (cached hints), and TL-C (full coherence) variants. **NoC Architecture** - **Topology**: Mesh (2D grid of routers — scalable, regular), ring (simpler but bandwidth-limited), tree (hierarchical, good for memory hierarchy), or custom topologies optimized for the specific SoC's traffic pattern. - **Router Design**: Each router has input buffers, a crossbar switch, and arbitration logic. Virtual channels (VCs) prevent head-of-line blocking by allowing multiple independent flows to share a physical link. - **Quality of Service (QoS)**: Priority-based arbitration ensures latency-sensitive traffic (display controller's frame reads, real-time audio) is serviced within deadline, even under heavy background traffic. **Cache Coherence** Multi-core SoCs require hardware coherence to maintain a consistent view of memory across all CPU caches. The interconnect implements a coherence protocol (MOESI, MESI) through snoop filters, directories, or broadcast snooping. The coherence traffic and snoop latency are often the performance bottleneck in many-core designs. On-Chip Interconnect Architecture is **the nervous system of the SoC** — carrying every instruction fetch, data load, DMA transfer, and coherence transaction between the processing elements that would be isolated and useless without it.