open fault
**Open Fault** in IC testing refers to an unintended break in an electrical connection, creating a high-impedance or floating node instead of the designed low-impedance path.
## What Is an Open Fault?
- **Cause**: Missing via, cracked metal, lifted bond, under-etching
- **Behavior**: Floating nodes, intermittent failures, stuck-at behavior
- **Detection**: IDDQ testing, transition delay test, connectivity test
- **Contrast**: Opposite of short/bridge faults (extra connections)
## Why Open Fault Detection Matters
Opens are harder to detect than shorts because floating nodes may capacitively couple to correct values, causing test escapes that fail in the field.
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**Testing Strategies for Opens**:
| Method | Coverage | Limitation |
|--------|----------|------------|
| Stuck-at ATPG | Partial | Miss weak opens |
| Transition delay | Good | Requires two-pattern |
| IDDQ | Excellent | Slow, needs quiescent |
| Open-specific ATPG | Best | Complex pattern generation |