Parametric Test

Parametric test measures electrical characteristics to determine whether semiconductor processing produced the intended devices and interconnects. Instead of asking whether a complete chip executes its functions, it asks focused questions: what gate voltage produces a defined transistor current, how much a junction leaks, or what resistance a contact chain presents. Those measurements connect physical processing to electrical behavior.

The test structure makes the question measurable. Dedicated transistors, capacitors, resistors, diodes, and contact structures expose useful terminals through probe pads. They may occupy scribe lanes or other allocated monitor areas. Their geometry and surroundings matter: a monitor represents particular process features, not automatically every device on the wafer. Keep structure identity, wafer coordinates, process step, and test-program revision attached to the data.

Force a condition, measure the response. A source-measure unit (SMU) can apply voltage while measuring current, or apply current while measuring voltage. Multiple channels establish transistor terminal biases; switching hardware connects them to the selected pads. Capacitance measurements require appropriate AC measurement capability rather than just a DC sweep. A test definition includes temperature, settling time, sweep direction, ranges, and extraction method, not merely a parameter name.

The probe connection can masquerade as the process. A two-wire resistance result includes voltage drops in the current-carrying leads and contacts. A properly implemented Kelvin connection senses voltage close to the device terminals through separate, very-low-current paths, reducing those external contributions. It does not erase resistance inside the selected sense points or repair a bad contact. Verify pad contact and the actual sense geometry before interpreting a resistance shift as a fabrication change.

A parameter is an extraction rule applied to data. For example, a constant-current threshold method reports the gate voltage where drain current reaches a specified criterion at defined drain and body biases. The criterion may include device-geometry normalization. A linear-extrapolation method can return a different value on the same device. Consequently, comparing threshold voltages requires the same method and conditions; the apparent shift may otherwise be a change in the measurement definition.

Compliance is not a valid result at the requested bias. A voltage-source SMU can limit current; a current-source SMU can limit voltage. When that limit is reached, the instrument may no longer deliver the programmed condition. Store the compliance status and actual measured values, and flag affected extractions. A clipped sweep can look like a device characteristic unless the test software checks instrument status. Limits help constrain exposure, but do not replace the system's safety provisions or device-specific qualification.

Small currents expose the measurement environment. Leakage through cables, switching hardware, contaminated fixtures, or the probe card can compete with the device current. Shielding, guarding, clean connections, and adequate settling are therefore part of the test method. Guarding and shielding perform different functions; they are not interchangeable wiring labels. Changing range or bias can introduce transients, and a shorter wait may improve nominal throughput while producing a less settled reading. Check repeatability and appropriate background measurements before declaring a leakage excursion.

Control limits and specification limits answer different questions. Specification limits describe required performance. Statistical control limits describe expected behavior of an established, stable process or monitored statistic. A measurement can satisfy specification yet signal a process change. Conversely, a stable process can be poorly centered or too variable to meet requirements. Use the chart appropriate to the data and sampling structure; do not substitute product limits for statistically established control limits.

Sampling defines what the result supports. Wafer acceptance testing (WAT) and process-control monitoring (PCM) use electrical evidence within a fab's qualification and production-control plans. Names and execution points vary. Not every structure is measured on every wafer, and test duration depends on sites, parameters, settling, and hardware. Record the sample plan, retain spatial maps as well as summaries, and avoid presenting a passing monitor sample as proof that every product die passes functional test.

Investigate the measurement chain before changing the process. An outlier can originate in the wafer, a poor probe contact, temperature error, a changed extraction rule, or an instrument problem. Preserve the original result and any retest history. Correlate confirmed shifts with relevant process measurements and tool history, using the established hold-and-disposition procedure. Parametric test is most useful when the measured quantity, its uncertainty, and the resulting decision remain traceable from the probe pad to the lot record.

Sources: Keysight, Parametric Test Solutions and B1500A Wafer Prober Connection Guide; Tektronix/Keithley, Low Current Measurement Optimization and 4200-SCS Reference Manual; NIST/SEMATECH, Control Charts and Process Capability; Generalized Constant Current Method for Determining MOSFET Threshold Voltage. Diagrams are explanatory, not test recipes or acceptance limits.