parametric yield loss

**Parametric Yield Loss** is **yield loss caused by devices failing to meet electrical performance specifications** — die that are physically intact (no killer defects) but whose transistors, resistors, or other components fall outside parametric limits (speed, power, leakage, voltage margins). **Parametric Yield Loss Sources** - **Vth Variation**: Threshold voltage outside specification — too much variation across the die. - **Leakage**: Excessive off-state leakage current — die fails power consumption specification. - **Speed**: Logic path delay exceeds timing target — die fails to meet target frequency (speed binning). - **Analog**: Amplifier gain, offset, or matching outside specification — critical for analog/mixed-signal products. **Why It Matters** - **Binning**: Parametric yield determines the distribution across speed/power bins — higher bins command premium pricing. - **Process Variability**: Driven by process variation (CD, implant dose, film thickness) — tighter variation improves parametric yield. - **Design Centering**: Optimizing the process center point to maximize the fraction of die in target bins. **Parametric Yield Loss** is **working but not good enough** — die that are defect-free but fail to meet performance specifications due to process variability.