parasitic extraction

**Parasitic Extraction (PEX/RCX)** is the **calculation of resistance and capacitance from layout geometry — accounting for metal width, thickness, spacing, and substrate coupling — converting layout into electrical models for post-layout timing/power simulation — enabling accurate timing closure and noise analysis at advanced nodes**. Parasitic extraction is essential for sign-off accuracy. **Resistance and Capacitance Extraction Fundamentals** Resistance is calculated from conductor geometry: R = ρ × (length / cross-section), where ρ is resistivity (Ω·cm), length is conductor length (cm), and cross-section is width × thickness (cm²). Resistance increases ~2x from 28 nm to 7 nm nodes due to: (1) thinner metal (reduced cross-section), (2) surface scattering effects (increased resistivity for narrow wires). Capacitance is more complex: (1) parallel-plate capacitance to substrate (C = ε·A/d, where ε is permittivity, A is area, d is thickness), (2) lateral fringing capacitance to adjacent wires, (3) coupling capacitance between net (to neighboring nets on same layer or adjacent layers). Total capacitance can be 2-3x larger than parallel-plate estimate due to fringing. **3D Field Solver Extraction** 3D field solvers (e.g., Ansys, Silvaco) solve Maxwell's equations numerically to accurately compute capacitance from detailed 3D geometry. Solver discretizes space around conductors, assigns boundary conditions, and solves for electric field and capacitance. Advantages: (1) accurate (captures 3D effects like fringing), (2) physics-based (no approximations), disadvantages: (1) slow (hours per net in tight geometries), (2) requires detailed geometry (all surrounding metal, vias, substrate). Field solvers are used for: (1) characterization (build parasitic tables for common geometries), (2) critical net validation (high-speed signals, sensitive paths). **Rule-Based Extraction** Rule-based extraction uses lookup tables and formulae to calculate capacitance from simple 2D information (layer, width, spacing, length). Extraction rules are derived from field solver or physics: examples: (1) parallel-plate cap to substrate = ε×W×L/t, (2) fringing cap = f(W, spacing, thickness) from empirical table, (3) coupling cap = f(spacing, length) from lookup. Rule-based extraction is fast (~seconds per circuit) and adequate for most nets. However, accuracy depends on quality of rules (typically ±10-20% error on tight geometries). Most production designs use rule-based extraction with field-solver validation for critical nets. **Coupling Capacitance and Crosstalk** Coupling capacitance between adjacent nets on same layer or adjacent layers is a significant component of total capacitance. High coupling capacitance enables crosstalk: aggressor net switching couples charge into victim net, causing noise spikes (glitches). Coupling capacitance grows with: (1) smaller metal pitch (closer spacing), (2) longer parallel overlap, (3) higher coupling factor (k = C_coupling / C_total, larger k = worse crosstalk). Extraction must account for coupling to all neighboring nets (not just nearest neighbors), as 2-3 neighbors can significantly contribute. Coupling extraction requires layout context: same net geometry in different regions (different neighbors) has different total capacitance. **Fringe Capacitance** Fringe capacitance is the electric field fringing at edges of parallel-plate conductors. Standard formula (C = ε×A/d) assumes uniform field; actual field fringing adds ~30-50% extra capacitance. Fringing scales with geometry: wider spacing reduces fringing (field more confined), narrower spacing increases fringing (field spreads). At aggressive pitches (40-50 nm), fringing can dominate total capacitance, making accurate extraction critical. **SPEF Format and Exchange** SPEF (Standard Parasitic Exchange Format) is industry-standard ASCII format for parasitic data: (1) net-by-net listing, (2) for each net: resistance (R branches), capacitance (C to ground, CC coupling between nets), (3) includes hierarchical structure. SPEF is human-readable and tool-portable. Tools (STA, simulation) read SPEF and use parasitics for timing/power. SPEF file size can be large (100 MB - 1 GB for full-chip), requiring compression or streaming for management. **QRC (Quadrature RC) Extraction** QRC (Cadence proprietary tool) is an industry-leading PEX tool: (1) fast (seconds to minutes for full-chip), (2) accurate (field-solver-like accuracy using optimized algorithms), (3) hierarchical (handles blocks and hierarchy efficiently). QRC combines rule-based (for fast execution) and field-solver validation (for accuracy at critical nodes). QRC is integrated with Innovus; alternative tools: StarRC (Synopsys), ArcPro (others). QRC results are typically signed-off for timing/noise closure. **Extraction Accuracy vs Speed Trade-off** Fast extraction (rule-based) sacrifices some accuracy (~5-15% error) for speed. Accurate extraction (field-solver based) takes longer but is more trustworthy for critical paths. Design sign-off often uses: (1) full-chip fast extraction for STA/power (global view), (2) detailed extraction (field-solver) for critical paths, high-speed nets, (3) coupling analysis separately (identify crosstalk risks). Iterative refinement: if timing is tight, more accurate extraction is performed. **RCXT for Post-Layout Simulation** RCXT (resistance-capacitance extraction) includes timing-aware effects: (1) crosstalk coupling delays (aggressor-to-victim delay variation), (2) frequency-dependent effects (resistance increases with frequency due to skin effect), (3) temperature-dependent R (resistance increases ~0.4%/K). RCXT tools provide detailed parasitic models for SPICE simulation. Post-layout SPICE simulation with RCXT is accurate but slow; used selectively for critical analog circuits or noise-sensitive paths. **Summary** Parasitic extraction translates physical layout into electrical models, enabling accurate post-layout verification and optimization. Continued advances in extraction algorithms and tools drive improved closure and sign-off confidence.