parasitic extraction
**Parasitic extraction** is the EDA process of computing the unintended resistance (R), capacitance (C), and inductance (L) of every wire, via, and device terminal in a chip's physical layout — numbers that are invisible in the schematic but dominate real-world performance at advanced nodes. A 10 mm wire at 5 nm has ~500 ohms of resistance and ~0.5 pF of capacitance that don't appear in the original netlist; without extraction, timing analysis would be off by 50–100% and the chip would fail at speed. Parasitic extraction transforms an idealized netlist into a physically-accurate model that sign-off tools (STA, power, SI) can trust.
**What "parasitics" are.** In a schematic, a wire is a zero-resistance, zero-capacitance ideal conductor. In real silicon, every metal segment has:
- **Resistance (R):** proportional to length, inversely proportional to cross-sectional area. At sub-20 nm widths, Fuchs-Sondheimer size effects raise Cu resistivity 3–5x above bulk (see the CFS copper-interconnect keyword).
- **Capacitance (C):** between the wire and every neighboring conductor — adjacent wires (coupling cap), wires above/below (plate cap), and the substrate. Determines RC delay and crosstalk.
- **Inductance (L):** significant only for wide, long wires at high frequency (power grid, clock distribution, I/O buses). Creates Ldi/dt voltage noise.
**The extraction equation.** For a single wire segment, the parasitic RC creates a distributed transmission-line delay approximated by:
$$\tau_{\text{50\%}} \approx 0.38 \cdot R_{\text{total}} \cdot C_{\text{total}} = 0.38 \cdot \frac{\rho \cdot L}{W \cdot T} \cdot (C_{\text{gnd}} + C_{\text{coupling}}) \cdot L$$
For a typical M1 wire at 5 nm (width 14 nm, length 100 um): $R$ ~ 500 ohm, $C$ ~ 0.5 pF, delay ~ 95 ps — comparable to multiple gate delays. This is why BEOL RC — not transistor speed — limits frequency at advanced nodes.
**Extraction accuracy levels:**
| Mode | What is computed | Accuracy | Runtime | Use case |
|---|---|---|---|---|
| R-only | Resistance of each wire segment | Low (timing rough) | Minutes | Early estimation, IR-drop |
| RC (lumped) | One R and one C per net | Medium | Minutes | Post-synthesis estimation |
| RC (distributed) | Multi-segment RC pi/T models per net | High (±3–5%) | Hours | STA sign-off, SI analysis |
| RLC | R + C + L (frequency-dependent) | Highest | Many hours | High-speed I/O, power grid |
| Field-solver | 3D electromagnetic solve per structure | Reference | Days | Calibration, custom structures |
**How extraction tools work.** The extraction engine (Synopsys StarRC, Cadence QRC/Quantus, Siemens Calibre xRC) reads the physical layout (GDS or DEF), the technology file (layer stackup: thickness, spacing, dielectric k-values per layer), and computes capacitance and resistance for every net:
1. **Geometry processing:** Identify all conductors and dielectrics in the cross-section around each net.
2. **Pattern matching:** For each wire segment, look up precomputed capacitance coefficients from a library of canonical 2D/3D structures (calibrated against field-solver reference).
3. **Resistance computation:** Segment the wire into pieces, compute R per segment from resistivity, width, thickness, via resistance.
4. **Coupling identification:** Find all neighboring nets within the interaction radius and compute mutual capacitance.
5. **Output:** A SPEF (Standard Parasitic Exchange Format) or DSPF file containing the RC network for every net — consumed by STA and power tools.
**Coupling capacitance and crosstalk.** At tight metal pitches (20–28 nm), the coupling capacitance between adjacent wires can exceed the ground capacitance. This means a switching neighbor can inject voltage noise into a quiet victim wire (crosstalk), causing timing violations. Extraction must compute both the total capacitance AND the per-aggressor coupling caps so that signal-integrity analysis can check crosstalk-induced delta-delay.
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**Extraction at advanced nodes — what changes.** At 5 nm and below: (1) coupling capacitance exceeds ground capacitance at the tightest pitches — crosstalk dominates; (2) via resistance becomes significant (each via is ~5–20 ohm at M1); (3) multi-patterning creates metal-line asymmetry that extraction must capture; (4) back-end low-k damage from etch raises effective k and must be modeled. Total extraction runtime for a full GPU at 3 nm: 24–72 hours on a large compute farm.
**Parasitic extraction and the CFS platform.** The CFS Interconnect Simulator at /interconnect models the Fuchs-Sondheimer resistivity and distributed RC delay that extraction computes. The low-k dielectric keyword covers the capacitance environment. The electromigration keyword covers the current-density limits that extraction-derived currents are checked against. Together they represent the physical reality that separates a schematic from a working chip.