parasitic extraction rcl

**Parasitic Extraction** is the **post-layout analysis process that computes the resistance (R), capacitance (C), and inductance (L) of every metal wire, via, and device interconnection in the physical layout — converting the geometric shapes of the routed design into an electrical RC/RCL netlist that accurately models signal delay, power consumption, crosstalk, and IR-drop for timing sign-off, power analysis, and signal integrity verification**. **Why Parasitic Extraction Is Essential** At advanced nodes, interconnect delay exceeds transistor switching delay. A 1mm wire on M3 at the 5nm node has ~50 Ohm resistance and ~50 fF capacitance, contributing ~2.5 ps of RC delay per mm — comparable to a gate delay. Without accurate parasitic modeling, timing analysis would be wildly optimistic, and chips would fail at speed. **What Gets Extracted** - **Wire Resistance**: Depends on metal resistivity, wire width, length, and thickness. At sub-20nm widths, surface and grain-boundary scattering increase effective resistivity by 2-5x above bulk copper. - **Grounded Capacitance (Cg)**: Capacitance between a wire and the reference planes (VSS, VDD) above and below. Depends on wire geometry and ILD thickness/permittivity. - **Coupling Capacitance (Cc)**: Capacitance between adjacent wires on the same or neighboring metal layers. Dominates at tight pitches — Cc is 50-70% of total capacitance at sub-28nm metal pitches. - **Via Resistance**: Each via has contact resistance (0.5-5 Ohm/via at advanced nodes). Via arrays in the power grid contribute significantly to IR-drop. - **Inductance**: Important only for wide global buses and clock networks where inductive effects (Ldi/dt) cause supply noise. Typically extracted only for selected nets. **Extraction Methods** - **Rule-Based**: Pre-computed lookup tables map geometric configurations (wire width, spacing, layer stack) to parasitic values. Fastest method (~1-2 hours for full chip) but limited accuracy for complex 3D geometries. - **Field-Solver Based**: Solves Maxwell's equations (or Laplace's equation in the quasi-static approximation) for the actual 3D geometry of each extracted region. Most accurate (1-2% error vs. measured silicon) but 5-10x slower than rule-based. - **Hybrid**: Rule-based for most of the chip, field-solver for critical nets. The production standard for sign-off extraction. **Extraction Accuracy vs. Silicon** Extraction tools are calibrated against silicon measurements (ring oscillator delays, interconnect test structures). The acceptable correlation error for sign-off is <3-5% for delay and <5-10% for capacitance across all metal layers and geometries. Parasitic Extraction is **the translation layer between geometry and electricity** — converting the physical shapes drawn by the place-and-route tool into the electrical models that determine whether the chip meets its performance, power, and signal integrity specifications.