physical verification signoff

**Physical Verification Signoff** — the comprehensive set of checks that must all pass before a chip design is approved for manufacturing (tapeout), ensuring the layout is correct and manufacturable. **Mandatory Signoff Checks** - **DRC (Design Rule Check)**: All layout geometries comply with foundry rules. Must be 100% clean - **LVS (Layout vs. Schematic)**: Physical layout matches intended circuit. Must be 100% clean - **ERC (Electrical Rule Check)**: No floating gates, shorted supplies, missing connections - **Antenna check**: No charge accumulation during manufacturing that could damage gate oxides - **Metal density check**: All layers within min/max density for CMP uniformity **Timing Signoff** - **STA (Static Timing Analysis)**: All paths meet setup and hold timing across all PVT corners (may be 50+ corners) - **SI (Signal Integrity)**: Crosstalk effects don't cause timing or functional failures - **IR drop**: Voltage drop within acceptable limits everywhere on chip **Reliability Signoff** - **EM (Electromigration)**: All wires and vias within current density limits for expected chip lifetime - **ESD**: Complete discharge paths verified for all pins **Power Signoff** - Power estimation at target workloads within thermal budget - Power-up/power-down sequences verified **Tapeout is a gate** — all signoff checks must pass with zero waivers for critical violations. A single missed check can result in non-functional silicon worth millions in wasted masks and months of delay.