PCIe

**PCIe (PCI Express)** is the high-speed serial interconnect that attaches almost every performance device inside a computer — GPUs, NVMe SSDs, network cards, and accelerators — to the CPU. It replaced the old shared parallel PCI bus with a switched fabric of independent point-to-point links, and it has become the backbone standard that other interconnects build on: NVMe runs over it, and CXL literally reuses its physical layer. For AI systems, PCIe is the road that feeds data to and from GPUs, and its bandwidth is often the thing standing between the accelerators and the rest of the machine.\n\n```svg\n\n```\n\n**PCIe is point-to-point and switched, not a shared bus.** Each device gets its own dedicated link to the root complex (in the CPU) or to a PCIe switch, so devices do not contend for a common bus the way legacy PCI did. This gives every endpoint full, predictable bandwidth and lets the topology scale out as a tree of links and switches rather than a single bottleneck.\n\n**Bandwidth is built from lanes.** A single lane is a pair of differential wires in each direction — a full-duplex serial connection. Links are assembled from 1, 4, 8, or 16 lanes (written x1, x4, x8, x16), and bandwidth scales almost linearly with lane count, which is why GPUs take a x16 slot while a modest SSD is happy with x4. The serial, differential design is what lets each lane run at multi-gigahertz rates over a cheap connector.\n\n**Each generation roughly doubles the per-lane rate.** From Gen1's 2.5 GT/s to Gen3's 8, Gen4's 16, Gen5's 32, and Gen6's 64 GT/s, the transfer rate has doubled about every generation. A x16 Gen5 link delivers on the order of 64 GB/s in each direction. Gen6 changes the signaling from simple on/off (NRZ) to four-level PAM4 to keep doubling the rate without doubling the clock, borrowing a trick from high-end SerDes.\n\n**It is layered like a network protocol.** PCIe organizes communication into a transaction layer (the read/write/message requests software cares about), a data-link layer (sequence numbers, acknowledgments, and retries for reliability), and a physical layer (the SerDes, encoding, and electrical signaling on the wire). This layering is why PCIe can guarantee reliable, ordered delivery while still running at extreme serial speeds.\n\n**PCIe is the foundation other standards extend.** NVMe defines how SSDs talk over PCIe; CXL adds cache coherence and memory semantics on top of the same PCIe electricals; many accelerators and even some chip-to-chip links reuse PCIe PHYs. Understanding PCIe lanes, generations, and topology is therefore the entry point to understanding most of the interconnect stack around modern compute.\n\n| Generation | Per-lane rate | ~x16 each way | Signaling |\n|---|---|---|---|\n| Gen3 | 8 GT/s | ~16 GB/s | NRZ |\n| Gen4 | 16 GT/s | ~32 GB/s | NRZ |\n| Gen5 | 32 GT/s | ~64 GB/s | NRZ |\n| Gen6 | 64 GT/s | ~128 GB/s | PAM4 |\n\nRead PCIe through a *lanes-and-generations* lens rather than a *slot* lens: a device's real throughput is the product of how many lanes it negotiates and which generation both ends support, and a fast GPU in a link-starved slot (too few lanes or an older generation) is quietly bottlenecked. Because NVMe and CXL ride on the very same physical layer, the lane budget and generation of your PCIe fabric set the ceiling for storage, memory expansion, and accelerator feeding alike.\n