Planar 1959 Step 14 Oxide Layer Parasitic Capacitance

# Pay for the Covered Junction With a Parasitic Capacitance the Mesa Transistor Never Had: The Cost Step 8 Did Not Measure

## 1. Why Keeping the Junction Covered Also Means Running Metal Over an Insulator That Is Not Free

Step 8 compared this series against the 1958 mesa baseline purely on reliability, where the planar device won decisively; this step runs a different comparison, on a property where the planar device actually loses something, because the field oxide and the metal interconnect routed across it in Step 6 together form a parallel-plate capacitor between that metal and the silicon underneath, a structure the mesa transistor's bare, etched sidewall never had the geometry to form. Any conductor separated from the substrate by a dielectric carries this capacitance automatically, scaling directly with the area the metal overlaps and inversely with how thick the separating oxide is — which means the exact field oxide this series relies on for isolation and protection is simultaneously setting a parasitic element that did not exist in the device Step 1 replaced.

$$C_{\text{ox,parasitic}} = \varepsilon_{\text{ox}}\,\frac{A_{\text{overlap}}}{x_{\text{ox}}}, \qquad f_{3\text{dB}} \propto \frac{1}{R_{\text{source}}\,C_{\text{ox,parasitic}}}$$

where $A_{\text{overlap}}$ is the area of metal routed over field oxide rather than directly over active silicon, and $x_{\text{ox}}$ the field-oxide thickness Step 12's furnace schedule produced. Every interconnect run Step 6 drew across the chip now has a frequency response bounded by this capacitance in series with whatever source resistance drives it — a limitation invisible to Step 8's reliability test, because a failure rate and a bandwidth measure two entirely different things about the same device.

Every Interconnect Run Doubles as a Capacitor Plate metal, field oxide, silicon — the same stack that protects the junction also stores charge metal interconnect, routed from step 6 field oxide, thickness x₂₅₝ silicon substrate, acting as the second plate A overlap, the span this capacitor actually spans C = εox · Aoverlap / xox — a structure the mesa sidewall never had the flat geometry to form step 8 measured a win on reliability; this is the column where the ledger runs the other way

## 2. Real Diagram: Trading Oxide Thickness Against Capacitance the Way Step 12 Already Traded It Against Masking Density

The same field-oxide thickness Step 12 chose for masking adequacy and mechanical robustness sets this capacitance in the opposite direction: a thicker oxide lowers parasitic capacitance but was already shown, in Step 12, to cost furnace time to grow by the slower, denser dry process this series prefers for its outer layers.

Thicker Oxide Helps Capacitance, Costs Furnace Time the same tradeoff step 12 named for masking, read again for interconnect speed parasitic capacitance, falls as oxide thickens furnace time required, rises as oxide thickens cost oxide thickness no single field-oxide thickness minimizes both columns at once; a layout has to pick a point and accept both costs

## 3. Why This Cost Was Always Priced Into the Same Decision Step 1 Made

Step 1's decision to leave the masking oxide in place rather than etching it away is the same decision that put a dielectric layer under every interconnect run this series has drawn since Step 6. That decision bought the reliability gain Step 8 measured and, in the same motion, introduced a capacitive load the mesa transistor's bare sidewall structurally could not form, because a conductor running over open air with no oxide beneath it has no comparable overlap capacitor to speak of. This is not a flaw in Step 1's reasoning; it is the first cost this series has had to admit against its own central decision, rather than another column of benefit.

Step 14 does not reverse anything this series has argued; it is the first step to price the planar surface's one unavoidable tax, owed on every run of metal this series has drawn across it since Step 6.

Take planar 1959 step 14 oxide layer parasitic capacitance further

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