power gating

Power gating shuts off power supply to idle circuit blocks by inserting high-Vt sleep transistors between the block and supply/ground rails, eliminating both dynamic and leakage power during standby. Architecture: (1) Header switch—PMOS sleep transistor between VDD supply and block virtual VDD; (2) Footer switch—NMOS sleep transistor between block virtual VSS and ground; (3) Combined—both header and footer for maximum isolation. Sleep transistor design: (1) High-Vt—minimizes leakage through switch itself when off; (2) Sizing—must be large enough to supply peak current with minimal IR drop (<5% VDD); (3) Distribution—coarse-grain (single large switch) or fine-grain (distributed switches across block). Power gating sequence: (1) Save state—retention registers capture critical state; (2) Isolate outputs—clamp outputs to known values; (3) Assert sleep signal—turn off sleep transistors; (4) Standby—block powers down, leakage near zero. Wake-up: (1) De-assert sleep—ramp up power (controlled ramp to limit inrush current); (2) Wait for voltage stabilization; (3) Release isolation; (4) Restore state from retention registers. Design challenges: (1) Inrush current—sudden power-on creates large current spike (mitigate with daisy-chain or staggered turn-on); (2) Wake-up latency—microseconds to stabilize; (3) Retention registers—special cells that maintain state during power-off; (4) Isolation cells—prevent floating outputs from corrupting active logic. Implementation: power intent defined in UPF (Unified Power Format), verified with power-aware simulation, physical design handles switch placement and power grid. Essential technique for mobile, IoT, and datacenter chips where leakage power is a significant portion of total power budget.