power rail design
**Power Rail Design and IR Drop Analysis** is the **process of planning the VDD/VSS distribution network and verifying that power supply voltage remains within acceptable bounds throughout the chip** — preventing performance degradation and functional failure from excessive resistive voltage drop.
**What Is IR Drop?**
- $V_{drop} = I \times R_{power rail}$
- As current flows through resistive power rails → local supply voltage drops.
- $V_{local} = V_{nominal} - V_{drop}$
- Effect: Lower supply voltage → slower transistors → timing violations.
- 10% IR drop: Equivalent to chip running at ~90% speed → can fail at target frequency.
**Power Network Design**
**Power Ring**:
- Wide VDD and VSS rings around core perimeter → supplies current from pads.
- Typical width: 10–50μm on M8–M12 layers (thick, low-resistance upper metals).
**Power Mesh**:
- Grid of wide stripes in both X and Y directions on upper metal layers (M6–M12).
- Mesh pitch: 20–100μm depending on current density.
- Lower resistance → better IR drop.
**Power Rails in Standard Cell Rows**:
- M1 VDD/VSS rails: 1 track wide, run through every cell row.
- Via connections from M1 rails up to mesh stripes.
**IR Drop Analysis Flow**
1. **Static IR**: Use average current per cell. Faster, identifies worst-case regions.
2. **Dynamic IR**: Use switching current waveforms (from power characterization or simulation). More accurate.
3. **Tools**: Synopsys PrimeRail, Cadence Voltus, ANSYS RedHawk.
**EM (Electromigration) Check**
- Metal atoms migrate under high current density → voids → wire breaks.
- EM rule: $J < J_{max}$ where $J_{max}$ depends on metal, temperature, wire width.
- Check every power/signal wire segment against EM limits.
- Solution: Widen wires, add parallel vias, reduce switching frequency.
**IR Drop Fixing**
- Add more stripes/wider mesh.
- Add power vias (stitch vias) between mesh layers.
- Add decoupling capacitance near high-switching cells.
- Balance placement to spread current demand uniformly.
Power rail design and IR drop closure is **a critical signoff requirement for every chip** — insufficient IR drop margin causes parametric failures that appear only at high frequency or high temperature, making power integrity analysis as essential as timing analysis in the sign-off checklist.