pre-metal dielectric

**Pre-Metal Dielectric (PMD) Gap Fill** is the **deposition and planarization of a low-defect silicon dioxide layer between tungsten contact plugs — typically using undoped silicate glass (USG) via SACVD or HARP chemistry — enabling low-resistance interconnect and serving as an interlayer dielectric before metal routing**. PMD is essential for contact resistance control and interconnect reliability. **Undoped Silicate Glass (USG) SACVD** PMD is predominantly composed of USG deposited via sub-atmospheric CVD (SACVD) using TEOS (tetraethyl orthosilicate) source gas. SACVD operates at 680-750°C and atmospheric pressure below 1 torr, enabling conformal oxide deposition with good gap-fill characteristics at moderate thickness (800-1200 nm typical). USG (unmixed SiO₂) is preferred over PSG (phosphosilicate glass with P dopant) due to lower etch rate in HF and better thermal stability; PSG reflow can damage underlying contacts. **HARP and Flowable CVD Chemistry** High-aspect-ratio process (HARP) uses TEOS + ozone (O₃-TEOS SACVD) for improved gap fill. Ozone reaction is surface-reaction-limited (not diffusion-limited), enabling rapid fill of deep trenches and narrow gaps without pinholes. Typical gap fill AR is 4:1 to 6:1 (e.g., 800 nm depth, 150 nm width). Flowable CVD (FCVD) is an alternative: precursor vapor condenses and flows at moderate temperature (~150-300°C), filling voids via capillary action. FCVD achieves excellent gap fill but is slower than HARP. **PMD Thickness and Coverage** PMD thickness is typically 800-1200 nm, determined by the distance between contact plugs and the first metal layer (M1) or routing layer. Thicker PMD provides better dielectric isolation but increases parasitic capacitance (impacts timing). Coverage uniformity is critical: thin areas risk dielectric breakdown (pin-holes in oxide), while thick areas reduce available routing space. Thickness uniformity target is typically ±10% across die. **CMP Planarization of PMD** After SACVD deposition, PMD is planarized via chemical-mechanical polishing (CMP) to remove topography and expose tungsten plug tops. PMD CMP uses silica-based slurries (SiO₂ abrasive particles ~20-100 nm diameter) with alkaline chemistry. Polishing pads and pressure are tuned to preferentially remove oxide over W (selectivity ~1:1 to 2:1, meaning W is removed at 50-100% of oxide rate — "soft polish"). Endpoint detection (optical or motor current change) stops when W is exposed. **Post-CMP Cleaning** After CMP, residual silica particles, metal contamination (Fe, Cu, W), and organic residues must be removed via chemical cleaning. Standard cleaning includes: dilute SC1 (0.1 M NH₄OH + H₂O₂, removes organic and metal particles), dilute HF dip (removes oxide residue), deionized water rinse, and isopropanol dry. Incomplete cleaning leaves particle residues that cause metal bridge shorts or via resistance increase. **PMD Doping and Gettering** In some processes, PMD is partially doped with phosphorus (PSG, 1-5 wt% P) to getter mobile ions (Na⁺, K⁺) that can cause device leakage. However, phosphorus lowers PMD density and etch rate, complicating CMP endpoint control. Modern processes minimize P doping due to process complexity; ion implantation gettering or guard ring design is preferred for ion mitigation. **Thermal Budget and Junction Compatibility** PMD deposition temperature (680-750°C) is lower than earlier metal deposition steps but still substantial. Thermal budget must be managed to avoid: (1) dopant diffusion in source/drain junctions (boron in p+, phosphorus in n+), (2) metal migration (Al, Cu), and (3) interface reactions. For advanced nodes with shallow junctions, lower-temperature PMD processes (PECVD-based) may be preferred, accepting reduced gap fill and requiring thinner PMD. **PMD Parasitic Capacitance** PMD between metal lines contributes to parasitic capacitance. Thinner PMD reduces capacitance (τ = RC decreases); however, too-thin PMD risks dielectric breakdown. Typical PMD contributes ~30-40% of total interlayer capacitance in older nodes, reducing in modern FinFET nodes due to larger metal pitches and air gap introduction. **Summary** PMD gap fill is a foundational process in interconnect technology, transitioning from contact plugs to metal routing. Continued optimization in SACVD/FCVD chemistry, CMP selectivity, and planarization enables reliable, low-parasitic interconnect at all technology nodes.