redistribution layer for tsv
**Redistribution Layer (RDL)** is a **thin-film metal wiring layer fabricated on the surface of a die or wafer that reroutes electrical connections from their original pad locations to new positions** — enabling fan-out of tightly spaced chip I/O pads to a wider-pitch bump array compatible with the substrate or next-level interconnect, and providing the backside wiring that connects revealed TSV tips to micro-bumps or hybrid bonding pads in 3D integration.
**What Is a Redistribution Layer?**
- **Definition**: One or more layers of patterned metal traces (copper) and dielectric insulation (polyimide, PBO, or inorganic) fabricated on a wafer or die surface using thin-film lithography and plating processes, creating a routing network that translates between the chip's native pad layout and the package's required bump pattern.
- **Fan-Out**: RDL extends connections from the die edge outward beyond the die footprint — fan-out wafer-level packaging (FOWLP) uses RDL to redistribute I/O from a small die to a larger package area, increasing the number of connections without increasing die size.
- **Fan-In**: RDL routes connections from peripheral pads to an area array under the die — converting a wire-bond pad layout to a flip-chip bump array without redesigning the chip.
- **Backside RDL**: In 3D integration, RDL on the thinned wafer backside connects revealed TSV tips to micro-bumps or bonding pads — this backside RDL is the critical wiring layer that enables electrical connection between stacked dies.
**Why RDL Matters**
- **I/O Density**: Modern SoCs require 5,000-50,000+ I/O connections — RDL enables routing this many connections from the chip's pad pitch (40-100 μm) to the package's bump pitch (100-400 μm) or to fine-pitch hybrid bonding pads (< 10 μm).
- **FOWLP**: Fan-out wafer-level packaging (TSMC InFO, ASE/Daishin) uses RDL as the primary interconnect — Apple's A-series and M-series processors use InFO-WLP with multi-layer RDL for high-density packaging.
- **3D Backside Connection**: After TSV reveal, the backside RDL provides the routing from TSV tips to the bonding interface — without RDL, each TSV would need to align directly with a pad on the next die, which is impractical.
- **Cost Reduction**: RDL-based packaging (FOWLP, fan-in WLP) eliminates the need for expensive ceramic or organic substrates in many applications, reducing package cost by 20-50%.
**RDL Process and Materials**
- **Dielectric**: Polyimide (PI), polybenzoxazole (PBO), or inorganic SiO₂/Si₃N₄ — provides insulation between RDL metal layers and passivation of the die surface. Polymer dielectrics are preferred for their low stress and thick-film capability.
- **Metal**: Copper deposited by sputtering (seed) + electroplating (bulk) — patterned by photolithography and etching or by semi-additive plating (SAP) where copper is plated only in photoresist openings.
- **Line/Space**: Production RDL achieves 2/2 μm line/space for advanced FOWLP — pushing toward 1/1 μm for next-generation high-density fan-out.
- **Layer Count**: 1-4 RDL layers for standard FOWLP, up to 6-8 layers for high-density applications — each layer adds routing capacity but increases cost and process complexity.
| RDL Application | Line/Space | Layers | Dielectric | Pitch |
|----------------|-----------|--------|-----------|-------|
| Fan-In WLP | 5-10 μm | 1-2 | PBO/PI | 200-400 μm bump |
| Standard FOWLP | 5-10 μm | 2-3 | PBO/PI | 200-400 μm bump |
| High-Density FOWLP | 2-5 μm | 3-6 | PBO/PI | 100-200 μm bump |
| TSV Backside | 2-5 μm | 1-2 | SiO₂/PI | 40-100 μm μbump |
| Interposer | 2-5 μm | 2-4 | SiO₂ | 40-100 μm μbump |
**Redistribution layers are the essential routing technology that bridges the gap between chip-level and package-level interconnect pitches** — providing the thin-film wiring that fans out dense chip I/O to package bumps, connects TSV tips to bonding interfaces, and enables the wafer-level packaging architectures that deliver the I/O density and cost efficiency demanded by modern semiconductor products.