Retention Register Sleep Mode

# Retention Register

Power gating a block means disconnecting its main supply entirely, and an ordinary flip-flop with no power simply loses whatever it was storing — fine for logic that's fully reset on wake-up, useless for anything that needs to resume exactly where it left off. A retention register solves that by splitting the flip-flop into two parts that don't share the same fate: a main storage element that loses power and its contents right along with the rest of the domain, and a small shadow latch wired to a separate always-on supply that keeps the stored bit alive through the entire power-down period.

The shadow latch only has to hold one bit, which is exactly why it costs so little area relative to the power it saves. A full flip-flop, kept always-on just to preserve state, would cost the same area and leakage as any other always-on flip-flop — defeating much of the point of power-gating the domain around it in the first place. A retention register instead adds a minimal shadow element, often a single small latch, specifically sized to do nothing but hold its one bit stable through power-down; it isn't actively computing or switching during that period, just sitting there drawing the small leakage current an always-on rail still has to supply. That asymmetry — a full flip-flop's worth of logic going dark, a tiny shadow latch staying lit — is the entire reason retention registers deliver real power savings instead of just moving the problem around.

Save and restore both have to be sequenced correctly relative to the power switch itself, with the same kind of strict ordering isolation cells already need around the same domain boundary. A save-trigger signal has to capture the main flip-flop's value into the shadow latch before the power switches actually cut supply — too late, and the main flip-flop has already lost its data before the shadow latch could copy it. On wake-up, the restore operation has to wait until the main domain's supply has fully stabilized before writing the shadow latch's held value back into the now-repowered flip-flop — too early, and the restore happens into a flip-flop that isn't electrically ready to hold it reliably. Power-aware verification checks this save/restore sequencing with the same rigor it checks isolation-cell timing, because a sequencing bug here doesn't cause a crash — it silently corrupts the state a block resumes with, which can be far harder to debug than an outright failure.

Retention registers trade real area and complexity for the ability to skip a full re-initialization on every single power-gating cycle, which only pays off when wake-up frequency and re-init cost both justify it. A block that power-gates rarely, or one whose logic resets cleanly to a known state on every wake-up anyway, often doesn't need retention registers at all — ordinary flip-flops and a full re-initialization sequence are simpler and cheaper. Retention registers earn their keep specifically on blocks that power-gate frequently and would otherwise pay a real latency or energy cost re-establishing state from scratch every single time — the tradeoff calculus a power-architecture team works out block by block, not a default applied uniformly across a whole chip.

Isolation cells (3144) prevent a power-gated domain's floating outputs from corrupting its always-on neighbors. Retention registers solve the complementary problem inside the domain itself — not containing the damage power-down causes, but avoiding it entirely for the specific bits of state a block needs to resume exactly where it left off.