semiconductor
**Semiconductor Deposition Processes** are the **thin film fabrication techniques that add layers of conducting, insulating, and semiconducting materials onto wafer surfaces** — forming the transistor gates, metal interconnects, dielectric insulators, and barrier layers that constitute modern integrated circuits, with each deposition method (CVD, PVD, ALD, epitaxy) optimized for specific materials, thicknesses, conformality, and temperature requirements across the hundreds of deposition steps in an advanced node process flow.
**What Are Deposition Processes?**
- **Definition**: Manufacturing techniques that deposit thin films (angstroms to micrometers thick) of materials onto semiconductor wafers — creating the layered structures that form transistors, capacitors, interconnect wiring, and insulating barriers in integrated circuits.
- **Additive Process**: Deposition is the primary additive step in semiconductor manufacturing — while lithography defines patterns and etching removes material, deposition adds the material layers that become functional circuit elements.
- **Film Requirements**: Deposited films must meet stringent specifications for thickness uniformity (< 1% across 300mm wafer), composition, stress, adhesion, step coverage (conformality in trenches and vias), and defect density — all controlled through precise process parameters.
- **Hundreds of Steps**: A modern logic chip at 3nm requires 300-500 deposition steps — each depositing a specific material at a specific thickness with specific properties, making deposition the most frequently performed process category in chip fabrication.
**Major Deposition Methods**
- **CVD (Chemical Vapor Deposition)**: Reactive gases flow over the heated wafer and chemically react on the surface to form a solid film — the workhorse deposition method for dielectrics (SiO₂, Si₃N₄), metals (W, TiN), and semiconductors. Variants include PECVD (plasma-enhanced, lower temperature), LPCVD (low-pressure, better uniformity), and MOCVD (metal-organic, for III-V compounds).
- **PVD (Physical Vapor Deposition)**: Material is physically transferred from a solid source to the wafer — sputtering (ion bombardment ejects atoms from a target) is the primary PVD method, used for metal films (Al, Cu seed, Ti, TiN, Ta, TaN) and barrier layers. Directional deposition with poor step coverage.
- **ALD (Atomic Layer Deposition)**: Self-limiting surface reactions deposit exactly one atomic layer per cycle — alternating precursor pulses build films with angstrom-level thickness control and perfect conformality in high-aspect-ratio structures. Essential for gate dielectrics (HfO₂), spacers, and advanced patterning.
- **Epitaxy**: Crystalline film growth that extends the wafer's crystal structure — used for SiGe source/drain stressors, Si channel layers, and III-V compound semiconductors (GaN, GaAs). Molecular beam epitaxy (MBE) and chemical vapor deposition epitaxy are the primary methods.
**Deposition Method Comparison**
| Method | Materials | Thickness Control | Conformality | Temperature | Throughput |
|--------|-----------|------------------|-------------|-------------|-----------|
| PECVD | SiO₂, SiN, SiC | ±2% | Moderate | 200-400°C | High |
| LPCVD | SiN, Poly-Si, SiO₂ | ±1% | Good | 400-800°C | Medium |
| PVD/Sputter | Metals, barriers | ±3% | Poor (directional) | 25-300°C | High |
| ALD | HfO₂, Al₂O₃, TiN | ±0.5% (atomic) | Perfect | 100-400°C | Low |
| Epitaxy | Si, SiGe, GaN | ±1% | N/A (blanket) | 500-1200°C | Low |
| MOCVD | GaN, InP, GaAs | ±2% | Good | 500-1100°C | Medium |
| ECD (Electroplating) | Cu, Sn, Au | ±5% | Good (with seed) | 25°C | High |
**Key Deposition Parameters**
- **Deposition Rate**: Film thickness deposited per unit time — ranges from 0.1 Å/cycle (ALD) to 1000+ nm/min (PECVD). Higher rates improve throughput but may sacrifice film quality.
- **Uniformity**: Thickness variation across the wafer — < 1% for critical films, controlled by gas flow distribution, temperature uniformity, and chamber geometry.
- **Step Coverage**: Ratio of film thickness on sidewalls to film thickness on top surface — critical for filling trenches and vias. ALD provides ~100% step coverage; PVD provides < 20%.
- **Film Stress**: Deposited films have intrinsic stress (tensile or compressive) — excessive stress causes wafer bow, cracking, or delamination. Controlled by deposition temperature, pressure, and plasma power.
**Equipment Vendors**
- **Applied Materials**: PECVD (Producer), PVD (Endura), Epi (Centura), ALD (Olympia).
- **Lam Research**: PECVD (VECTOR), ALD (ALTUS), ECD (SABRE).
- **Tokyo Electron (TEL)**: CVD, ALD, epitaxy systems.
- **ASM International**: ALD (Pulsar), PECVD, epitaxy — leading ALD market share.
**Semiconductor deposition processes are the additive foundation of chip manufacturing** — building the hundreds of thin film layers that form transistors, interconnects, and insulators through precisely controlled CVD, PVD, ALD, and epitaxy techniques, with each method optimized for the specific material, conformality, and thickness requirements of modern integrated circuit fabrication.