sequential

**Sequential 3D Integration** is **stacking sequential silicon layers via epitaxy and bonding on single substrate for monolithic 3D circuits** — true integration without post-CMOS assembly. **Layer Growth** silicon epitaxy deposits crystalline silicon atop first layer dielectric. **Epitaxy Temperature** silicon growth ~600-800°C; below copper reflow (~800°C). Process selection critical. **Silicon Quality** epitaxial silicon may have defects; gettering and annealing improve. **Gate Sequencing** gate-first: pattern gates, subsequent layers. Gate-last: maximum flexibility, higher complexity. **Oxide Interface** Si-SiO₂ interface quality critical (Dit, Nss); engineering improves interface. **Via Metallurgy** tungsten or copper vias connect tiers. Silicide formation, contact resistance important. **Planarization** CMP after each layer growth before next deposition. **Interconnect Distribution** traditional single-tier multiple metals → distributed across tiers. Fewer layers per tier. **Via Density** sub-100 nm vias possible at advanced nodes. **Lithography** each layer requires alignment (~50 nm overlay tolerance). **Defect Impact** first-layer defects foundational; yield concern. **Manufacturing Variation** temperature, pressure, contamination affect yield. **Stress Migration** metal EM reduced from shorter wires. Benefit. **Thermal Dissipation** stacked transistors generate heat; lower tiers dissipate upward. **Seq-3D enables monolithic stacking** with integrated sequential layer processing.