shallow trench isolation

**Shallow Trench Isolation (STI)** is **a front-end-of-line isolation technique that physically separates active transistor regions by etching narrow trenches into the silicon substrate and filling them with deposited oxide, followed by chemical-mechanical planarization (CMP) to achieve a flat surface** — replacing the older LOCOS method that suffered from bird's beak encroachment and poor scalability below 250 nm nodes. STI delivers tighter transistor pitch, superior planarity, and better latch-up immunity across modern CMOS technologies. - **Trench Etch**: A pad oxide and silicon nitride hard mask define the active areas; reactive-ion etching (RIE) creates trenches typically 250-350 nm deep with near-vertical sidewalls and a slight taper angle of 83-87 degrees to promote void-free filling. - **Liner Oxidation**: A thin thermal oxide liner of 5-10 nm is grown on the trench sidewalls to heal etch damage, passivate interface states, and round the top corners to reduce electric field crowding that can cause parasitic leakage. - **Trench Fill**: High-density plasma chemical vapor deposition (HDP-CVD) or sub-atmospheric CVD (SACVD) deposits silicon dioxide to fill the trench without voids; advanced nodes use flowable CVD (FCVD) oxide that converts spin-on precursors into high-quality SiO2 through steam annealing, enabling gap fill at aspect ratios exceeding 10:1. - **CMP Integration**: Oxide CMP removes excess fill material and stops on the nitride hard mask; slurry chemistry is tuned for high oxide-to-nitride selectivity (typically greater than 30:1) to prevent dishing of wide trenches and erosion of dense active areas. - **Dishing and Erosion Control**: Dummy fill patterns are inserted in layout-sparse regions to equalize pattern density across the die, keeping local and global planarity within 20-50 nm specification windows required by subsequent lithography. - **Divot Management**: After nitride strip in hot phosphoric acid, a recess or divot forms at the STI-to-active boundary; excessive divots expose the silicon corner and create parasitic edge transistors with lower threshold voltage, so controlled oxide recess etching limits divot depth to below 5 nm. - **Stress Effects**: The STI oxide exerts compressive stress on the channel region, which benefits PMOS hole mobility but degrades NMOS electron mobility; stress engineering through liner nitride films or adjusted fill densities can mitigate these asymmetries. STI process control remains critical at every node because isolation integrity, surface planarity, and stress uniformity directly impact transistor matching, leakage, and yield across the entire wafer.