shallow trench isolation basics

**Shallow Trench Isolation (STI)** — the standard technique for electrically isolating adjacent transistors on a chip by etching shallow trenches and filling them with oxide. **Process** 1. Deposit pad oxide + silicon nitride hard mask 2. Pattern and etch trenches into silicon (~300-500nm deep) 3. Grow thin thermal oxide liner to repair etch damage 4. Fill trench with HDP (High-Density Plasma) oxide or flowable CVD oxide 5. CMP to planarize and remove excess oxide, stopping on nitride 6. Strip nitride to expose active silicon areas **Why STI?** - Replaced LOCOS (Local Oxidation of Silicon) at 250nm node - No bird's beak encroachment — tighter transistor spacing - Better planarity for subsequent lithography - Scalable to advanced nodes **Challenges** - STI stress affects transistor mobility (can be used advantageously for strain engineering) - Divot formation at STI edges during wet cleaning - Void-free fill becomes harder at sub-10nm feature widths **STI** is one of the first steps in CMOS fabrication — it defines where each transistor lives on the wafer.