shallow trench isolation (sti) stress

**STI Stress** is the **mechanical stress exerted on the silicon channel by the adjacent Shallow Trench Isolation structures** — arising from the thermal expansion mismatch between the SiO₂ fill and the silicon substrate during high-temperature processing. **What Causes STI Stress?** - **CTE Mismatch**: SiO₂ ($alpha approx 0.5$ ppm/°C) vs. Si ($alpha approx 2.6$ ppm/°C). After cooling from deposition temperature, the oxide is under compression and exerts stress on the silicon. - **Stress Type**: Compressive along the channel direction near STI edges. - **Effect on Mobility**: Compressive stress boosts hole mobility (good for PMOS) but degrades electron mobility (bad for NMOS). **Why It Matters** - **Intentional Exploitation**: Modern processes intentionally engineer stress (strained silicon) to boost mobility. - **Unintentional Variation**: STI stress varies with device geometry (LOD effect, narrow-width effect). - **Scaling**: As devices shrink, STI edges get closer to the channel, amplifying the stress effect. **STI Stress** is **the silent force shaping transistor performance** — a mechanical influence that can either help or hurt depending on the device type and geometry.