Channel Release Sacrificial Sige
# SiGe Selective Etch and Nanosheet Channel Release
A gate-all-around transistor gets its name from the gate wrapping completely around the channel on all four sides, but the channel doesn't start out as a free-standing sheet with room for a gate to wrap around it. It starts as one layer in a stack of alternating silicon and silicon-germanium grown epitaxially on top of each other, with the SiGe layers acting purely as sacrificial spacers. Channel release is the step that removes those SiGe layers selectively, undercutting them out from underneath and above each silicon sheet until every channel layer is left suspended, held only at its two ends, with open space all the way around where the gate stack will go next.
The whole process depends on an etch chemistry that attacks SiGe aggressively while leaving the silicon layers essentially untouched, and that selectivity is what makes the entire GAA architecture manufacturable. A wet or dry etch tuned for very high Si:SiGe selectivity — commonly based on a chemistry that exploits germanium's different oxidation and etch-rate behavior relative to pure silicon — removes the SiGe layers laterally, eating inward from every exposed edge of the stack, while the silicon nanosheet layers sandwiched between them barely etch at all. Get that selectivity wrong and the process either fails to fully clear the SiGe (leaving residual sacrificial material blocking the gate from wrapping all the way around) or starts attacking the silicon channel itself, thinning or damaging the very structure the whole device depends on.
Inner spacer formation has to happen before the release etch, specifically to protect the source/drain regions from the exact same SiGe-attacking chemistry doing the channel release. The SiGe layers don't just sit under the gate — they extend out toward the source and drain regions too, and the eventual source/drain epitaxy needs those same SiGe-adjacent regions to form properly contacted junctions. Inner spacers, a dielectric film deposited specifically into the small recess left after an earlier partial SiGe etch at the source/drain edge, shield that junction region from the full channel-release etch that comes later, preventing the aggressive SiGe-selective chemistry from also attacking material the device still needs intact. Getting inner spacer thickness and placement right is a tight tolerance problem in its own right — too thin and it fails to protect the junction during release, too thick and it eats into the channel length or source/drain volume the device actually needs.
Suspended-sheet stiction — released sheets sagging or sticking to each other or to the sheet above/below during the subsequent wet processing — is this process's own version of the same collapse risk fin structures face. Once the SiGe is fully removed, each silicon sheet is only mechanically anchored at its two ends, exactly the free-standing, weakly-supported geometry that makes any subsequent wet clean a capillary-collapse risk — the same underlying physics as fin bending (id 607) and resist pattern collapse (id 562), now acting on a structure suspended on both top and bottom rather than standing on a base. Process integration specifically sequences the post-release clean and dry steps, and controls release-etch depth and sheet spacing, to keep stiction risk manageable before the gate stack goes down and locks each sheet's final position in permanently.
STI divot and bird's beak lose silicon at an isolation edge; fin collapse and now nanosheet stiction lose devices to the same capillary mechanism acting on progressively more exposed, more suspended silicon geometry as the industry has moved from planar to FinFET to GAA. Channel release is the step that creates that exposed geometry in the first place — the direct structural reason GAA transistors inherit fin collapse's failure mode and then make it worse.