Sige-Sacrificial-Layer

A SiGe sacrificial layer is a temporary silicon-germanium alloy layer designed to be selectively removed during fabrication. In a common silicon nanosheet transistor flow, epitaxy alternates retained silicon channels with sacrificial SiGe. Removing the SiGe opens space around the channels for gate dielectric and metal. The temporary layer’s thickness, composition and interfaces therefore influence the finished transistor even though that layer is absent from the released gate region.

Build the material stack
Grow Si / SiGe
Control thickness and alloy
Preserve interfaces
Manage strain and heat
Use the sacrificial regions
Form spacer pockets
Recess selected SiGe at ends
Release the channels
Remove SiGe in gate cavity
Complete and verify
Deposit gate stack
Surround retained Si sheets
Check the device
Residue, geometry and leakage

The temporary layer helps set the vertical geometry. The SiGe/Si superlattice establishes alternating material regions before patterning. Silicon thickness helps define the retained channel body, while sacrificial-layer thickness helps establish the separation between channels after removal. IBM’s AiMES 2018 presentation explicitly connects the sacrificial SiGe to this suspension spacing. Gate dielectric, work-function materials and the integrated release process then occupy or modify that available space. The drawing shows a conceptual three-sheet example, with no proprietary layer count or dimensional specification.

SiGe Sacrificial Layers Define the Gate Space The temporary alloy helps establish the spaces between the retained silicon channels. Si / SiGe epitaxial stack After release and gate fill Substrate / isolation Substrate / isolation Si channel SiGe Removed later G Release + gate formation G illustrates the original sacrificial-layer thickness; final gaps depend on the integrated process. Green: retained Si · gray: sacrificial SiGe · cyan: gate dielectric · amber: gate metal Transverse gate-cavity sections; source/drain anchors are out of the page. Geometry is not to scale.

Alloy composition affects both growth and removal. SiGe is commonly written Si(1−x)Ge(x), where x represents the germanium atomic fraction. Changing composition alters the lattice relationship to silicon and the response to a chosen etch chemistry. A useful stack must balance epitaxial quality, layer thickness, strain and selective-removal behavior. IBM’s multilayer research discusses composition, interface abruptness and relaxation; its selective-etch work studies germanium-content dependence. A reported composition in one experiment should retain that context rather than becoming a universal requirement for every nanosheet process.

Two fabrication modules use the removable material differently. During inner-spacer formation, a controlled lateral recess creates pockets near the stack ends that are subsequently filled with dielectric. During channel release, sacrificial material is removed from the gate region to expose the channels for a surrounding gate. IBM’s research describes both uses. Their purposes and removal extents differ, so an inner-spacer recess depth is not a specification for complete channel release. Protective structures and the source/drain connections must survive the relevant operations.

Interface quality and thermal history carry forward. Interdiffusion can blur the original Si/SiGe boundary, changing the material encountered by a later selective etch. Layer uniformity and prior processing therefore influence the final silicon thickness and the released gap. IBM describes precise epitaxial thickness control as a nanosheet advantage, while Seoul National University’s study analyzes how finite selectivity and release exposure change channel geometry and electrical behavior. Qualification must connect the grown stack to the structure after the complete process sequence.

SiGe can also be a retained device material. Sacrificial describes a process role, not an inherent property of every SiGe region. For example, a pFET can use SiGe source/drain epitaxy that is intended to remain while sacrificial SiGe is removed from the gate cavity. IBM’s 2023 source/drain-damage study examines this integration challenge. Spacer coverage, release chemistry and protective layers help distinguish the regions that should be removed from those that need protection. The compact longitudinal section below makes these different material roles visible.

The Same Alloy Can Have Different Process Roles A material’s location and function determine which regions are removed and which must survive. SiGe S/D retain SiGe S/D retain Sacrificial SiGe: remove from gate region Illustrative pFET material roles · purple: protective inner spacers · green: Si channels

Verification follows the material through to the working transistor. As-grown thickness, composition, crystal quality and interface profiles are starting measurements. After recess and release, inspection checks residual sacrificial material, channel thinning, gap dimensions and damage to protected regions. Subsequent gate formation and electrical characterization test whether the material choices support the required performance, leakage and reliability. Etch selectivity alone does not establish this complete result. Comparisons need the material pair, geometry, exposure and measurement conditions, rather than a single alloy fraction or nominal removal rate.

Sources and further reading. [IBM AiMES 2018: SiGe/Si superlattice epitaxy and sacrificial-layer spacing](https://ecs.confex.com/ecs/aimes2018/webprogram/Paper113422.html); [IBM IEDM 2019: composition-sensitive selective SiGe removal](https://research.ibm.com/publications/a-novel-dry-selective-etch-of-sige-for-the-enablement-of-high-performance-logic-stacked-gate-all-around-nanosheet-devices); [IBM on nanosheet thickness control and integration](https://research.ibm.com/blog/nanosheet-technology-ai-5g); [Seoul National University: channel-release effects on geometry and electrical behavior](https://snu.elsevierpure.com/en/publications/investigation-of-electrical-characteristic-behavior-induced-by-ch/); [IBM SSDM 2023: protecting retained source/drain epitaxy](https://research.ibm.com/publications/epi-sourcedrain-damage-mitigation-with-inner-spacer-and-buffer-optimization-in-stacked-nanosheet-gate-all-around-transistors).

Read the SiGe sacrificial layer as a temporary material with lasting consequences: grow the required geometry, remove the intended regions selectively, and verify the channels and devices that remain.

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