Sige Superlattice Etch
The SiGe superlattice stack etch cuts a single continuous opening through an epitaxially grown stack of alternating silicon and silicon-germanium layers, and it produces a scalloped sidewall ripple that looks superficially like the TSV's Bosch-process texture covered earlier in this project — except here that ripple is an unwanted artifact process engineers have to suppress, not a deliberately engineered profile they're trying to produce. Silicon-germanium etches faster than pure silicon in most standard halogen-based plasma chemistries, because the weaker silicon-germanium bond gives the etch less resistance to work against, so cutting straight through a stack that alternates between the two materials naturally produces a wavy sidewall where each SiGe layer recedes slightly faster than the silicon layers above and below it unless the chemistry is specifically tuned to erase that rate difference.
The deliberate-versus-unwanted distinction here is a direct inversion of the TSV round's Bosch process, which is worth stating explicitly because the resulting sidewall texture can look similar at first glance. The TSV etch's scalloping came from cyclically alternating etch and passivation steps on purpose, because that cycling was the only practical way to sustain a deep, controlled etch through bulk silicon; this superlattice etch runs as one continuous process, and any scalloping that shows up here is a sign the chemistry hasn't fully equalized the Si-versus-SiGe etch rate, which means engineers reading a cross-section of this structure have to know which kind of ripple they're looking at before concluding anything about whether the etch succeeded.
Both materials in this stack are destined to play specific, different functional roles later, which is a genuinely different relationship between the two etched materials than this project's earlier stacks have had — most notably setting up the sacrificial-SiGe technique the next round in this sequence will depend on directly. Unlike 3D NAND's alternating oxide-nitride stack, where one material is a structural placeholder and the other defines device function from the start, this silicon-germanium superlattice has both materials still semiconducting and both still candidates for an active role — but the SiGe layers specifically are grown with the expectation that a later step will selectively remove them, a sacrificial-epitaxial-layer technique borrowed directly from advanced logic gate-all-around nanosheet transistor manufacturing, where SiGe is grown between silicon channel layers for the explicit purpose of being etched away afterward to release the channel; this etch's job is simply to open the stack cleanly enough that the selective removal step covered in the next round has a well-defined, straight-walled structure to work with.
Read through a same-texture-opposite-verdict lens, the SiGe superlattice stack etch is where this project's emerging-architecture coverage has to borrow a visual pattern from an already-covered etch and immediately warn against reading it the same way twice — the ripple that proved the TSV's Bosch process was working correctly is the same shape that signals this etch's chemistry still needs tuning, which is exactly the kind of judgment call that separates a straightforward etch inspection from one that requires knowing the mechanism, not just the picture.