silicide

**Silicide Formation** is **the self-aligned process of reacting a deposited metal film with exposed silicon to create a low-resistivity metal silicide compound at the source, drain, and gate surfaces, dramatically reducing contact resistance between the transistor and the overlying interconnect metallization** — with nickel monosilicide (NiSi) and cobalt disilicide (CoSi2) being the most widely used phases in modern CMOS manufacturing. - **Salicide Process Flow**: The self-aligned silicide (salicide) process deposits a blanket metal film over the wafer, performs a first rapid thermal anneal (RTA) to form a metal-rich silicide phase, selectively strips unreacted metal from dielectric surfaces using wet chemistry, and then performs a second RTA to convert the silicide to its lowest-resistivity phase. - **NiSi Advantages**: Nickel monosilicide consumes less silicon per unit thickness than CoSi2, forms at lower temperatures (250-350 degrees Celsius for the first anneal), and does not exhibit the linewidth-dependent resistance increase that plagues CoSi2 on narrow polysilicon lines; NiSi sheet resistance remains below 10 ohms per square on features as narrow as 30 nm. - **CoSi2 Applications**: Cobalt disilicide offers excellent thermal stability up to 850 degrees Celsius and is preferred in high-temperature process flows; however, it requires a two-step anneal at 500 and 700 degrees Celsius and shows nucleation-limited growth on narrow lines that increases resistance. - **Platinum Alloying**: Adding 5-10 percent platinum to the nickel film improves NiSi thermal stability by suppressing the transformation to the high-resistivity NiSi2 phase, extending the process window for subsequent thermal steps and reducing agglomeration on thin silicon-on-insulator (SOI) substrates. - **Interface Preparation**: A pre-silicide clean using dilute HF and argon sputter removes native oxide from the silicon surface to ensure uniform metal-silicon reaction; poor surface preparation leads to high contact resistance, silicide voiding, and junction spiking. - **Contact Resistance Reduction**: Silicided junctions achieve specific contact resistivities of 1e-8 to 1e-7 ohm-cm2; further reduction employs high-dose implant-to-silicide (ITS) techniques where heavy dopant implantation into the silicide is followed by millisecond laser annealing to drive dopants to the silicide-silicon interface. - **Silicide Encroachment**: Lateral silicide growth along the silicon surface beneath the spacer must be controlled to prevent junction shorting; optimized metal thickness and anneal conditions limit lateral encroachment to less than 5 nm. Silicide engineering continues to evolve alongside contact architectures because the interface between the silicide and the silicon junction is often the dominant resistance bottleneck in aggressively scaled transistors.