silicide

**Silicide Process: NiSi and CoSi2 for Low Contact Resistance** is **metal silicide formation on silicon surfaces for source/drain and gate contacts — providing low contact resistivity, thermal stability, and integration with CMOS processing**. Silicides are metal-silicon compounds formed by reacting metals deposited on silicon. The low resistivity of silicides (typically 10-50 μΩ-cm) enables low contact resistance for transistor source/drain and gate connections. Historically, cobalt disilicide (CoSi2) dominated due to excellent properties. More recently, nickel monosilicide (NiSi) has become preferred for advanced technology due to lower processing temperature and better integration characteristics. CoSi2 formation occurs at high temperature (>900°C), enabling thermally stable contacts but consuming substantial silicon (CoSi2 requires specific Co:Si ratio, typically requiring ~500nm silicon consumption per 100nm silicide thickness). High temperature processing can damage underlying devices and cause dopant diffusion. NiSi forms at lower temperature (400-500°C), reducing thermal budget impact and silicon consumption. NiSi has lower resistivity at thin thicknesses compared to CoSi2. NiSi-platinum (NiSi-Pt) alloys further reduce resistivity. Salicide (Self-Aligned Silicide) process deposits metal on entire wafer after gate definition, selectively forms silicide on exposed silicon while metal remains or is removed from non-silicon surfaces. Careful processing ensures silicide forms only on source/drain and gate, not on sidewalls or poly. Silicide thickness control is critical — too thin provides excessive contact resistance, too thick consumes excess silicon and creates processing challenges. Typical NiSi thickness is 10-30nm. Metal-induced lateral crystallization (MILC) can reduce annealing temperature requirements for some silicides. Highly textured or amorphous silicon enables lower-temperature silicide formation. Nickel-induced crystallization particularly benefits from MILC. Process variations in silicide formation cause variations in contact resistance. Dopant concentration in source/drain regions affects silicide resistivity — higher doping reduces contact resistance. Dopant segregation at silicide/silicon interface requires careful modeling. Thermal stability determines device reliability — insufficient thermal stability causes silicide agglomeration and increased contact resistance over time. Kirkendall void formation (void generation at silicide/silicon interface due to different diffusion rates) can cause contact degradation. Additive elements (platinum, germanium) stabilize silicide against agglomeration. Silicide etch selectivity relative to dielectric materials and underlying silicon determines contact via formation. Etching must remove silicide from non-contact areas while preserving contact silicide. Oxide remaining on silicide prevents good silicide/metal contact if not removed. **Silicide contacts provide low contact resistance essential for advanced devices, with process choices (NiSi vs CoSi2) representing fundamental tradeoffs between processing temperature and contact properties.**