Silicon Gate 1967 Dope Polysilicon Gate Work Function

# Step 7 — Dope the Polysilicon Gate to Lower Its Resistance and Set Its Own Work Function: Degenerate Doping and the Threshold Voltage Dividend

## 1. How Heavy Doping Solves Resistance and Unlocks Low Threshold Voltages

Intentionally doping the polysilicon gate to degeneracy ($N_D > 10^{20}\ \text{cm}^{-3}$) achieves two revolutionary physical results at the exact same moment: it drives the gate sheet resistance down from hundreds of ohms per square to under $30\ \Omega/\Box$, and it moves the gate's Fermi level to the silicon conduction band edge, shifting the transistor's threshold voltage ($V_{\text{th}}$) into direct compatibility with 5-volt bipolar logic. In 1962's aluminum-gate process, the gate material was a fixed elemental metal with an unalterable work function of $\Phi_{\text{Al}} \approx 4.1\ \text{eV}$. That fixed metal work function, combined with unavoidable positive fixed oxide charges ($Q_{\text{ox}}$), locked metal-gate MOSFETs into high, awkward threshold voltages—often requiring $-3\ \text{V}$ to $-5\ \text{V}$ for p-channel devices and large counter-doping to prevent n-channel devices from staying normally-on. In this step, phosphorus or boron is driven into the polysilicon film to its solid-solubility limit. Because the gate is itself silicon, choosing its dopant type tunes its work function: an $n^+$ polysilicon gate pins the gate Fermi level at the silicon conduction band edge ($E_c$), reducing the magnitude of the threshold voltage by roughly $1.0\ \text{V}$ and enabling the device to switch crisply on standard low-voltage power supplies.

$$V_{\text{th}} = \Phi_{\text{MS}} - \frac{Q_{\text{ox}}}{C_{\text{ox}}} + 2\phi_F + \frac{\sqrt{2\varepsilon_{\text{Si}} q N_A (2\phi_F)}}{C_{\text{ox}}}, \qquad \Phi_{\text{MS}} = \Phi_{\text{gate}} - \Phi_{\text{substrate}}$$

where $\Phi_{\text{MS}}$ is the work function difference between the gate and the silicon substrate. For an $n^+$ polysilicon gate on a p-type substrate, $\Phi_{\text{gate}} \approx \chi_{\text{Si}} \approx 4.05\ \text{eV}$, which shifts $\Phi_{\text{MS}}$ substantially more negative than an aluminum gate. That negative shift directly cancels the positive threshold-voltage offset, dropping $V_{\text{th}}$ from 1962's unmanageable $3\text{--}5\ \text{V}$ down to a clean $1.0\text{--}1.5\ \text{V}$ window. Simultaneously, the free carrier density saturates the polysilicon grains, suppressing the sheet resistance and taming the distributed RC transmission line delay identified in Step 6.

Energy Band Alignment: Tuning the Work Function ΦMS degenerate n+ polysilicon pins the Fermi level at Ec, shifting threshold voltage down by ~1.0 V 1962: FIXED ALUMINUM WORK FUNCTION EF,Al ΦAl ≈ 4.1 eV SiO2 (Barrier) Ec EF,Si Ev ΦMS,Al ≈ -0.3 V → High Vth (3 to 5 V) Requires high supply voltages (12V–20V) 1967: DEGENERATE n+ POLYSILICON GATE EF,poly ≈ Ec Φn+poly ≈ 4.05 eV ND > 10²⁰ cm⁻³ SiO2 (Barrier) Ec EF,Si Ev ΦMS,poly ≈ -1.0 V → Low Vth (1.0 to 1.5 V) Compatible with 5V supplies and bipolar TTL ΔVth = ΦMS,poly - ΦMS,Al ≈ -0.7 V to -1.0 V Heavy gate doping simultaneously drops sheet resistance to <30 Ω/□ and brings Vth down to 1.2 V.

## 2. Real Diagram: Simultaneous Resistance Collapse and Threshold Shifting

Heavy doping transforms the polysilicon gate on two fronts: electrical resistivity drops by orders of magnitude while the switching threshold voltage moves directly into the 5V logic operating envelope.

Dual Benefits of Heavy Gate Doping (ND > 10²⁰ cm⁻³) sheet resistance suppression curves and the resulting transfer characteristic shift SHEET RESISTANCE SUPPRESSION Dopant Concentration (cm⁻³) → Rs (Ω/□) Undoped: >10⁴ Ω/□ Partial: ~300 Ω/□ Degenerate: 20–30 Ω/□ Saturating grain boundaries enables solid-solubility limit THRESHOLD VOLTAGE NORMALIZATION Gate-Source Voltage VGS (V) → Drain Current ID 1962 Al Gate (Vth ≈ 3.5 V) 1967 n+ Poly Gate (Vth ≈ 1.2 V) ΔVth ≈ -2.3 V Shift Operates directly at 5V logic without high-voltage bias supplies A material breakthrough that simultaneously conquered two distinct domain boundaries: Lowering Rs solves circuit bandwidth (Step 6), while tuning ΦMS enables direct interfacing with bipolar TTL logic.

## 3. Resolving the Voltage Barrier That Kept MOS Isolated

Throughout the early 1960s, despite its theoretical promises of extreme packing density and near-zero static power (established in the 1963 CMOS series), MOS technology remained trapped in an awkward circuit ghetto. Because aluminum's work function pushed threshold voltages up to 3V, 5V, or higher, MOS chips required cumbersome auxiliary power supplies (+12V, -20V) and could not interface directly with the dominant digital logic standard of the era: 5-volt bipolar Transistor-Transistor Logic (TTL).

Step 7 dismantled that voltage barrier forever:
1. The Work Function Revolution: By abandoning elemental metals in favor of degenerate polycrystalline silicon, semiconductor physicists gained control over the gate's work function. Setting $\Phi_{\text{poly}} \approx 4.05\ \text{eV}$ via heavy donor doping shifted the work function difference $\Phi_{\text{MS}}$ by approximately $-1.0\ \text{V}$, pulling the transistor's threshold voltage down into the pristine $1.0\text{--}1.5\ \text{V}$ window.
2. TTL Compatibility Achieved: With a 1.2V threshold voltage, a MOS inverter could switch reliably on a single 5-volt rail, accepting standard TTL logic highs (2.4V) and lows (0.4V) directly at its input pins without level-shifter circuits.
3. Quenching Gate Resistance: Simultaneously, doping the polysilicon to its solid-solubility limit saturated the grain boundary traps, collapsing sheet resistance to $20\text{--}30\ \Omega/\Box$. This tamed the transmission line delay analyzed in Step 6, ensuring that the self-aligned gate switched cleanly and rapidly across standard logic layouts.

Heavy gate doping turned the self-aligned silicon-gate transistor into a complete, self-consistent digital logic technology: fast, dense, and naturally compatible with the rest of the semiconductor world.

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