stacking faults

**Stacking Faults** are **planar crystal defects where the regular ABCABC stacking sequence of {111} atomic planes is locally disrupted** — they occur in epitaxial growth, ion implantation, and oxidation, and can produce catastrophic device leakage when they intersect active regions or become decorated with metallic impurities. **What Are Stacking Faults?** - **Definition**: A two-dimensional planar defect in which one or more atomic planes are either missing (intrinsic stacking fault: ABCABABC) or inserted (extrinsic stacking fault: ABCABCABC) relative to the perfect FCC-derived stacking sequence of silicon. - **Bounding Partial Dislocations**: A stacking fault is bounded by partial dislocation lines with Burgers vectors of the a/6 <112> type — the partial dislocations form a Frank partial (immobile, creating a faulted loop) or a Shockley partial (mobile, allowing fault growth by glide). - **Oxidation-Induced Stacking Faults (OISF)**: Thermal oxidation injects silicon interstitials into the substrate as it consumes silicon to form SiO2. These interstitials condense on pre-existing nucleation sites (contamination, scratches) and grow stacking faults that can extend micrometers into the wafer. - **Epitaxial Stacking Faults**: Particles, surface contamination, or substrate crystal defects present during epitaxial growth force the depositing silicon to adopt a mis-registered stacking sequence, propagating a fault upward through the grown layer. **Why Stacking Faults Matter** - **Image Sensor White Pixels**: A single stacking fault in the depleted photodiode region of a CMOS image sensor creates a high-leakage pixel (white pixel) that is permanently bright regardless of illumination — a critical killer defect for CIS yield. - **Metal Decoration**: Metallic impurities (copper, iron, nickel) have very low diffusion barriers along stacking fault planes and preferentially precipitate on faults, creating conductive paths through dielectric regions or junction regions that cause device failure. - **OISF Ring and Bulk**: Oxidation-induced stacking faults form preferentially in a ring pattern across the wafer at regions of intermediate oxygen concentration — the OISF ring is a key wafer quality indicator measured at every crystal qualification. - **Epitaxial Layer Quality**: Stacking faults that nucleate at the substrate-epitaxial interface and propagate to the device region cause local crystallographic disorder that disrupts transistor channel uniformity and creates leakage paths. - **Gettering Disruption**: While stacking faults can act as gettering sites, they compete with intentional gettering structures and can redistribute trapped impurities into harmful locations under subsequent thermal cycling. **How Stacking Faults Are Controlled** - **Wafer Surface Preparation**: Chemical-mechanical polishing, HF last cleaning protocols, and clean room particle control minimize nucleation sites for both epitaxial and oxidation-induced stacking faults. - **OISF Suppression**: Chlorinated oxidation with HCl addition neutralizes interstitial silicon injection and suppresses OISF nucleation — standard in all high-quality gate oxidation processes. - **Epitaxial Process Control**: In-situ HCl etching before epitaxial deposition removes surface contaminants that would nucleate stacking faults, combined with controlled temperature ramps to prevent thermal shock-induced nucleation. Stacking Faults are **crystallographic sequence errors that propagate through the device layer and attract metallic impurities** — their prevention through wafer quality, surface cleanliness, and process chemistry is essential for achieving the defect densities required by image sensor and advanced logic applications.