three dimensional ic stacking
**3D-IC Die Stacking** is the **advanced packaging technology that vertically stacks multiple silicon dies and interconnects them using Through-Silicon Vias (TSVs), micro-bumps, or hybrid bonding**, enabling higher bandwidth, lower power, and smaller footprint than traditional 2D designs by placing memory directly above logic or stacking heterogeneous technologies.
3D-IC represents a paradigm shift from scaling transistors smaller (More Moore) to scaling system integration vertically (More than Moore). HBM (High Bandwidth Memory) stacking DRAM dies above a base logic die is the most commercially successful 3D-IC technology, providing 1+ TB/s memory bandwidth.
**3D Integration Technologies**:
| Technology | Pitch | Density | Application |
|-----------|-------|---------|-------------|
| **TSV (Through-Silicon Via)** | 5-50um | 10K-1M/mm^2 | HBM, interposer |
| **Micro-bump** | 25-55um | ~400/mm^2 | Die-to-die in HBM |
| **Hybrid bonding (Cu-Cu)** | 1-10um | 1M-100M/mm^2 | CMOS image sensors, AMD 3D V-Cache |
| **Dielectric bonding** | N/A | N/A | Temporary carrier wafers |
| **Monolithic 3D** | <1um | Highest | Research (sequential integration) |
**TSV Design Considerations**: TSVs are vertical copper pillars (typically 5-10um diameter, 50-100um deep) that pass through the silicon substrate. Design challenges: **keep-out zone** (TSV stress affects nearby transistors — 5-20um exclusion zone around each TSV reduces available routing area), **capacitive loading** (TSV capacitance ~30-100fF adds to signal delay), **thermal** (TSVs conduct heat vertically but stacked dies have higher thermal resistance than single die), and **reliability** (thermal cycling stress from Cu-Si CTE mismatch can cause TSV cracking).
**Floor Planning for 3D**: Unlike 2D, 3D floorplanning must consider: **inter-die alignment** (TSV/micro-bump positions on top die must align with bottom die), **thermal stacking** (avoid stacking high-power blocks directly above each other), **power delivery** (TSVs carry power/ground vertically — allocate sufficient TSV count for IR drop), and **testability** (each die must be testable independently before stacking — KGD, Known Good Die).
**Hybrid Bonding**: The most advanced interconnect technology, enabling <1um pitch Cu-Cu direct bonding between dies at the wafer or die level. AMD 3D V-Cache uses hybrid bonding to add 64MB SRAM cache directly on top of the CPU die, providing a 3x cache size increase within the same package footprint. The density advantage over micro-bumps (100-1000x more connections per area) enables fundamentally different architectures.
**EDA Tool Support**: 3D-IC design requires extensions to traditional 2D tools: **3D-aware floorplanning** (block placement considering vertical connections), **inter-die timing analysis** (TSV/bump delay models in STA), **3D power integrity** (IR drop across stacked dies), **3D thermal analysis** (coupled thermal simulation of stacked dies), and **3D DRC/LVS** (cross-die connectivity verification).
**3D-IC die stacking is reshaping chip architecture beyond the limitations of transistor scaling — by building vertically, designers can achieve bandwidth, density, and heterogeneous integration impossible in any 2D design, making 3D the defining technology of the post-Moore era.**