through silicon via tsv

**Through-Silicon Via (TSV) Technology** is the **vertical electrical interconnect that passes completely through a silicon die — providing direct, short-path connections between stacked chips in 3D integration, with TSV diameters of 1-10 μm and depths of 50-100 μm enabling >10,000 connections per mm² between die layers, delivering the bandwidth density (10-100× greater than wire bonding or micro-bumps alone) required for HBM memory stacks, 2.5D interposers, and 3D stacked logic/memory architectures**. **TSV Fabrication Approaches** **Via-First**: TSVs formed before FEOL transistor processing. - Advantage: No thermal budget constraints. - Disadvantage: TSV must survive all subsequent processing (1000°C+ anneal). Limited to passive interposers (no transistors on the interposer, just routing). **Via-Middle**: TSVs formed after FEOL (transistors complete) but before BEOL (metal interconnects). - Typical approach for active die (logic, memory with TSVs). - TSV must survive BEOL processing (400°C max). - Most common for HBM DRAM and 3D logic integration. **Via-Last (from Backside)**: TSVs formed from the wafer backside after all front-side processing is complete. - Wafer thinned first, then TSVs etched from the back. - Advantage: No impact on front-side processing. - Disadvantage: Difficult alignment to front-side features through thinned silicon. **Via-Middle Process Flow** 1. **TSV Etch**: Deep reactive ion etch (DRIE) using Bosch process (alternating SF₆ etch and C₄F₈ passivation) creates high-AR blind holes in silicon. Diameter: 5-10 μm, depth: 50-100 μm (AR = 10:1). For advanced TSVs: 1-3 μm diameter, 10-30 μm deep. 2. **Liner Deposition**: SiO₂ insulation layer (1-2 μm by PECVD or thermal) to isolate the Cu TSV from the Si substrate. Prevents Cu diffusion into Si. 3. **Barrier/Seed**: TaN barrier + Cu seed (PVD) on the via sidewalls. 4. **Cu Electroplating**: Bottom-up superfill of the high-AR via using acid Cu sulfate electrolyte with accelerator/suppressor/leveler additives. Fill time: 30-120 minutes per wafer. 5. **CMP**: Remove Cu overburden above the surface. 6. **BEOL Fabrication**: Standard metal interconnect layers are built over the TSVs, connecting them to the circuit. 7. **Wafer Thinning (Backgrind)**: After BEOL, the wafer is bonded face-down to a carrier and thinned from the backside using mechanical grinding + CMP to expose the TSV Cu at the backside (TSV "reveal"). 8. **Backside Processing**: Deposit SiO₂ isolation, open TSV contact pads, deposit redistribution layer (RDL). **Keep-Out Zone (KOZ)** The area around each TSV where transistors cannot be placed: - Cu TSV induces thermo-mechanical stress in the surrounding Si (CTE mismatch: Cu = 17 ppm/°C, Si = 2.6 ppm/°C). - Stress affects transistor mobility and Vth. KOZ radius: 5-15 μm (process dependent). - KOZ represents lost silicon area — minimizing KOZ is critical for dense 3D integration. **HBM TSV Implementation** Each HBM stack uses ~5,000-10,000 TSVs per die: - Diameter: ~5-6 μm. Pitch: ~40-55 μm. Depth: ~50 μm. - 12-16 die stacked, each with TSVs aligned and connected via micro-bumps or hybrid bonds. - Bandwidth: 1024 bits wide × 8 Gbps = >1 TB/s per stack (HBM3E). TSV Technology is **the vertical highway system of 3D semiconductor integration** — the copper-filled pillars through silicon that provide the thousands of parallel electrical connections between stacked die, enabling the memory bandwidth and heterogeneous integration architectures that define the performance frontier of AI and high-performance computing.