through silicon via

**Through-Silicon Via (TSV) Fabrication and 3D Stacking** is **the process of creating vertical electrical connections that pass entirely through a silicon die or interposer, enabling multiple device layers to be stacked and interconnected in three dimensions** — TSV technology dramatically shortens interconnect length, reduces power consumption, and increases bandwidth compared with traditional 2D side-by-side integration. - **Via-First, Via-Middle, Via-Last**: TSVs can be formed before CMOS processing (via-first), after front-end but before back-end metallization (via-middle), or after the wafer is fully processed (via-last). Via-middle at 5–10 µm diameter is the mainstream approach for high-performance logic and HBM memory. - **Etch Process**: Deep reactive-ion etching (Bosch process) alternates SF6 etch and C4F8 passivation cycles to create high-aspect-ratio holes (10:1 or greater) with scalloped sidewalls that are later smoothed. - **Liner and Barrier**: A SiO2 isolation liner is deposited by PECVD or thermal oxidation, followed by a TaN/Ta barrier and Cu seed layer deposited by PVD or ALD to prevent copper diffusion into silicon. - **Copper Fill**: Bottom-up electroplating fills the via without voids using suppressor-accelerator-leveler additive chemistry. Superfill capability is critical for defect-free metallization. - **CMP and Reveal**: After plating, excess copper is removed by CMP at the wafer front side. The wafer is then thinned from the back side by grinding and CMP until TSV tips are exposed (via reveal), producing a wafer typically 50 µm thick. - **Bonding and Stacking**: Thinned wafers or dies are bonded using micro-bumps (Cu-pillar with solder caps), direct Cu-Cu thermocompression bonding, or hybrid bonding (oxide-oxide plus Cu-Cu). Hybrid bonding enables sub-1 µm pitch interconnects. - **Applications**: HBM DRAM stacks 8–12 die with TSVs; 2.5D interposers in AMD and NVIDIA GPUs carry chiplets on a silicon bridge; 3D NAND uses TSV-like structures for peripheral logic. - **Challenges**: TSV-induced thermo-mechanical stress creates keep-out zones around vias, wafer thinning and handling require temporary carrier bonding, and testing stacked die before final assembly is complex. TSV-based 3D integration is the foundational technology enabling high-bandwidth memory, heterogeneous chiplet architectures, and the continued scaling of system performance beyond Moore's Law.