through silicon via tsv

**Through-Silicon Via (TSV) Technology** is the **vertical interconnect method that creates electrical connections through the full thickness of a silicon die — enabling 3D IC stacking where multiple die layers communicate through thousands of high-density, short-distance vias rather than edge-routed wire bonds or package-level redistribution, providing 10-100x higher interconnect density and 10x lower power per bit compared to conventional 2D packaging**. **TSV Fabrication Approaches** - **Via-First (Before FEOL)**: TSVs etched and filled before transistor fabrication. High aspect ratio achievable but TSV materials must survive all subsequent high-temperature processing (~1000°C). Rarely used in practice. - **Via-Middle (After FEOL, Before BEOL)**: TSVs fabricated after transistors but before metal interconnect layers. The dominant approach for logic+memory 3D stacking. TSV dimensions: 5-10 μm diameter, 50-100 μm depth (aspect ratio 5:1 to 10:1). - **Via-Last (After BEOL, from Frontside or Backside)**: TSVs etched through the completed die from the wafer backside. Lower aspect ratio achievable. Used for interposers and image sensors. TSV dimensions: 10-50 μm diameter. **TSV Fabrication Process Flow (Via-Middle)** 1. **Etch**: Deep reactive ion etch (DRIE) using the Bosch process (alternating SF₆ etch and C₄F₈ passivation cycles) creates high-aspect-ratio vias with scalloped sidewalls. 2. **Insulation**: SiO₂ or SiN dielectric liner deposited by PECVD or thermal oxidation. Prevents copper diffusion into silicon and provides electrical isolation. Typical thickness: 100-500 nm. 3. **Barrier/Seed**: TaN/Ta barrier layer + Cu seed layer deposited by PVD. Prevents Cu diffusion through the oxide and provides nucleation for electroplating. 4. **Fill**: Bottom-up Cu electroplating using superfilling chemistry (accelerator/suppressor/leveler additives). Void-free fill of high-aspect-ratio vias is critical — any void becomes a reliability failure point. 5. **CMP**: Remove Cu overburden from the wafer surface. 6. **Reveal**: After BEOL completion, the wafer is thinned from the backside (grinding + CMP) until TSV tips are exposed. Final thickness: 50-100 μm. **TSV Reliability Concerns** - **Cu Pumping (Protrusion)**: Thermal cycling causes Cu to expand more than Si (CTE mismatch: Cu 17 ppm/°C vs. Si 2.6 ppm/°C), pushing Cu out of the via. Controlled by pre-annealing the Cu fill and limiting thermal excursions. - **Keep-Out Zone (KOZ)**: The stress field around each TSV (from CTE mismatch) affects nearby transistor mobility and threshold voltage. A 5-15 μm keep-out zone around each TSV is reserved — reducing available routing area. - **Electromigration**: High current density through small-diameter TSVs can cause Cu atom migration and void formation. Design rules limit current density to <2 MA/cm². Through-Silicon Via Technology is **the physical bridge between 2D and 3D semiconductor integration** — the enabling interconnect technology that makes die stacking, HBM memory, and advanced chiplet architectures possible by threading electrical connections vertically through silicon.