through silicon via tsv

**Through-Silicon Via (TSV)** is **the vertical electrical interconnect that passes completely through a silicon wafer or die — providing low-inductance, high-bandwidth connections between stacked dies in 3D integrated circuits with typical dimensions of 5-100μm diameter, 50-300μm depth, and resistance 10-100 mΩ per via**. **TSV Fabrication Approaches:** - **Via-First**: TSVs formed before transistor fabrication on blank wafers; vias etched 50-300μm deep, lined with isolation dielectric (SiO₂ 0.5-2μm), barrier/seed layer (Ta/Cu 50/200nm), and Cu electroplated; subsequent FEOL (front-end-of-line) processing builds transistors around the TSVs - **Via-Middle**: TSVs formed after FEOL but before BEOL metallization; enables optimization of TSV process without impacting transistor performance; via depth typically 50-100μm; BEOL metal layers connect transistors to TSV landing pads - **Via-Last**: TSVs formed after complete device fabrication from wafer backside; requires wafer thinning to 50-100μm before via etching; lowest thermal budget impact on devices but limited via depth by final wafer thickness; most common for memory stacking (HBM, HMC) - **Process Selection**: via-first offers deepest vias and best Cu fill but highest thermal budget; via-last minimizes device impact but limits via depth; via-middle balances both considerations; choice depends on application requirements and integration complexity **TSV Etching:** - **Bosch Process (DRIE)**: alternating SF₆ etch and C₄F₈ passivation cycles create high-aspect-ratio vias; typical parameters: 5-15 second etch, 3-7 second passivation, 100-300 cycles for 100μm depth; achieves aspect ratios 10:1 to 20:1 with sidewall angle 88-90° - **Scalloping**: Bosch process creates 50-200nm amplitude sidewall ripples; scallop size controlled by cycle time (shorter cycles = smaller scallops); excessive scalloping increases sidewall roughness causing Cu void formation during electroplating - **Etch Rate and Uniformity**: 2-5 μm/min etch rate with ±3% depth uniformity across 300mm wafer; Lam Research Syndion and Applied Materials Centura DRIE tools with multi-zone temperature control and endpoint detection - **Via Reveal**: after backside grinding, remaining Si at via bottom removed by timed etch or CMP; over-etch creates recessed Cu requiring redistribution layer (RDL) to make electrical contact; under-etch leaves Si residue causing high resistance **Dielectric Liner and Barrier:** - **Isolation Dielectric**: PECVD or ALD SiO₂ deposited 0.5-2μm thick on via sidewalls; provides electrical isolation between Cu fill and Si substrate; breakdown voltage >100 V/μm; capacitance 50-200 fF per via depending on diameter and liner thickness - **Barrier/Seed Layer**: PVD Ta/TaN (30-50nm) prevents Cu diffusion into Si; PVD Cu seed (100-300nm) provides nucleation layer for electroplating; conformal coverage on high-aspect-ratio sidewalls requires ionized PVD or ALD; Applied Materials Endura PVD with IMP (Ionized Metal Plasma) achieves <10% thickness variation from top to bottom - **Liner Stress**: thermal oxide (wet oxidation at 1000°C) provides lowest stress but high thermal budget; PECVD oxide has tensile stress 100-300 MPa; ALD Al₂O₃ or HfO₂ enables thinner liners (50-100nm) with better conformality but higher cost - **Leakage Current**: properly isolated TSVs exhibit <1 pA leakage at 1V bias; defects (pinholes, barrier discontinuities) cause leakage >100 nA; electrical test of every TSV required for high-reliability applications **Copper Filling:** - **Electroplating**: Cu electroplated from CuSO₄ electrolyte with organic additives (accelerator, suppressor, leveler) that enable bottom-up fill; current density 5-20 mA/cm² with plating time 2-6 hours for 100μm depth; Applied Materials Raider and Lam Research SABRE tools - **Superfilling**: additive chemistry creates faster plating at via bottom than sidewalls; prevents void formation in high-aspect-ratio structures; requires precise additive concentration control (±5%) and temperature (±1°C) for void-free fill - **Annealing**: post-plating anneal at 200-400°C for 30-120 minutes reduces Cu resistivity from 2.0-2.5 μΩ·cm (as-plated) to 1.7-1.9 μΩ·cm (annealed) by growing grain size from 0.5μm to 2-5μm; also relieves plating stress - **CMP**: overplated Cu removed by chemical-mechanical polishing; typical removal 5-20μm with <50nm dishing in large vias; KLA Tencor Candela optical profiler measures post-CMP topography; excessive dishing causes RDL connection failures **TSV-Induced Stress:** - **CTE Mismatch**: Cu thermal expansion (16.5 ppm/K) vs Si (2.6 ppm/K) creates radial stress during temperature cycling; stress extends 2-5× via diameter into surrounding Si; can shift transistor threshold voltage by 10-50 mV in keep-out zone - **Keep-Out Zone (KOZ)**: region around TSV where transistor placement is restricted; typical KOZ radius = 1-3× TSV diameter; reduces available Si area by 5-15% depending on TSV density; circuit design must account for KOZ in floorplanning - **Stress Mitigation**: annular TSV (hollow center) reduces stress by 30-50%; polymer liner (BCB, polyimide) absorbs stress but increases capacitance; optimized annealing profiles minimize residual stress Through-silicon vias are **the critical enabler of 3D integration — providing the vertical highways that carry power, ground, and signals between stacked dies with performance approaching on-chip interconnects, making possible the high-bandwidth, low-latency communication required for advanced 3D systems**.