Sti Divot

# STI Divot

Shallow trench isolation leaves a trench filled with oxide between active areas, polished flat by CMP so the next layer starts on a planar surface. That flatness doesn't survive the rest of the front end intact — by the time gate formation happens, the trench corner has recessed into a divot carved right along the active-area edge. The sequence that gets it there looks like this:

STI CMP
trench oxide polished flush with silicon
Wet-clean sequencepre-gate HF dip, sacrificial-oxide strips, liner cleans
Liner oxide etch
weaker than bulk fill oxide
Cumulative recess
a few angstroms per step, never refilled
↻ next wet step
Divot at gate formation
corner recessed below active-area silicon

The corner recesses faster than the field because the liner oxide underneath it is the weaker material. STI isn't solid oxide top to bottom — a thin thermal liner oxide grows on the trench sidewall and bottom before the bulk gap-fill oxide (typically a denser CVD or flowable-CVD film from a tool like Applied Materials' Producer or Centura platforms) goes in on top of it. Both are silicon dioxide chemically, but the liner, grown thin and often slightly more porous near the corner where growth kinetics are least uniform, etches measurably faster in dilute HF than either the bulk fill oxide or the silicon it's protecting. Every wet clean the wafer sees between STI CMP and gate formation removes a little more of that already-weaker liner right at the trench edge than it removes bulk silicon elsewhere — small losses per step, a few angstroms, but cumulative and directional, since nothing refills them.

How a Flush Trench Becomes a Divot repeated wet cleans etch the weaker liner oxide at the corner faster than bulk silicon AFTER STI CMP — flush trench oxide level with silicon active area STI fill AFTER WET CLEANS — divot oxide recessed below silicon surface active area corners exposed — this is where the gate will wrap

The divot turns one transistor into two. Gate poly and gate oxide deposit over this recessed geometry, not a flat one — at the active-area corner, the gate wraps down into the divot and around the corner of the silicon, effectively adding a second, parasitic transistor there with its own effective oxide thickness and its own threshold voltage. That corner device switches on at a lower gate voltage than the intended planar transistor, because the gate wrapping a convex silicon corner concentrates field lines there, and the measurable signature is a double-hump in the subthreshold I_D–V_G curve: current rises at the corner device's lower threshold, flattens briefly, then rises again at the main transistor's intended threshold. KLA-class inline defect-inspection tools catch the geometric recess directly; the double-hump itself shows up downstream on wafer-level electrical test.

The Double-Hump Signature of Divot-Driven Corner Leakage subthreshold current vs. gate voltage for a transistor with a divoted STI edge gate voltage → log(I_D) ideal, no corner device corner-device turn-on (low V_T) hump / plateau main transistor turn-on The hump's height tracks divot depth directly — it's a direct electrical readout of how much corner oxide was lost to wet-clean recess.

The process window controls it on both the materials side and the layout side. Denser liner and fill-oxide densification (a higher-temperature anneal after deposition) etches more slowly in dilute HF, directly cutting the per-clean recess rate; rounding the active-area mask corner itself spreads the field concentration over a radius instead of a point, softening the threshold shift even where some divot remains; process integration teams track total HF-equivalent dip time across the whole flow rather than any single clean, since the divot is cumulative across every wet step; and a thin nitride cap or stress liner at the corner, more HF-resistant than oxide, can hold the corner geometry through the sequence even as the field-region liner recesses normally.

End-of-range dislocation loops are damage buried inside the silicon from an implant. STI divot is a geometric problem at the silicon surface, inherited from the trench-fill process steps earlier — a reminder that threshold-voltage variation at advanced nodes comes as much from isolation geometry drifting through later wet chemistry as from the transistor's own implant and anneal recipe.

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