strained silicon

**Strained Silicon** is a **process technology that intentionally deforms the silicon crystal lattice** — stretching (tensile) or compressing it to change the band structure and increase carrier mobility, delivering 20-50% performance improvement without shrinking the transistor. **What Is Strained Silicon?** - **Tensile Strain (for NMOS)**: Stretches Si along the channel -> reduces electron effective mass -> higher electron mobility. - **Compressive Strain (for PMOS)**: Compresses Si along the channel -> modifies hole band structure -> higher hole mobility. - **Methods**: - **Global**: SiGe virtual substrate (biaxial strain). - **Local**: CESL liners (tensile for NMOS), embedded SiGe S/D (compressive for PMOS). **Why It Matters** - **Free Performance**: Mobility boost without voltage or dimension changes. - **Industry Standard**: Every node from 90nm onward uses deliberate strain engineering. - **Pioneered by Intel**: Intel's 90nm strained silicon (2003) was a landmark in transistor engineering. **Strained Silicon** is **bending the crystal for speed** — a brilliant exploitation of solid-state physics that gave Moore's Law a critical boost.