strain engineering

**Strain Engineering** — intentionally applying mechanical stress to the silicon channel to boost carrier mobility, a key performance enhancer since the 90nm node. **Physics** - Strain changes the silicon crystal lattice spacing - This modifies the band structure, reducing carrier effective mass - Result: Carriers move faster → higher transistor current without shrinking **Techniques** - **SiGe S/D for PMOS**: Epitaxially grown SiGe in source/drain regions compresses the channel. Boosts hole mobility 25-50% - **SiN Stress Liner for NMOS**: Tensile silicon nitride film deposited over transistor. Stretches the channel, enhancing electron mobility 15-20% - **STI Stress**: Shallow trench isolation edges exert stress on nearby channels - **Embedded SiC for NMOS**: Tensile stress from carbon incorporation (less common) **Dual Stress Liner (DSL)** - Tensile SiN liner over NMOS regions - Compressive SiN liner over PMOS regions - Each transistor type gets its optimal stress **Impact** - Equivalent to ~1 generation of scaling improvement for free - Intel introduced at 90nm (2003) — now universal - FinFET and GAA transistors continue to use strain engineering **Strain engineering** provided critical performance boosts during the era when pure geometric scaling slowed down.