thermocompression bonding
**Thermocompression Bonding (TCB)** is a **solid-state bonding technique that joins two metal surfaces by applying simultaneous heat and mechanical pressure** — causing atomic interdiffusion across the interface without melting either surface, creating a metallurgical bond with bulk-like electrical and thermal conductivity, widely used for gold-to-gold and copper-to-copper interconnections in flip-chip packaging, wire bonding, and advanced 3D integration.
**What Is Thermocompression Bonding?**
- **Definition**: A diffusion bonding process where two clean metal surfaces (typically Au-Au or Cu-Cu) are pressed together at elevated temperature (150-400°C) with controlled force (10-100 MPa), causing atoms at the interface to interdiffuse and form a continuous metallic bond without any liquid phase or filler material.
- **Atomic Diffusion**: At the bonding temperature, metal atoms gain sufficient thermal energy to diffuse across the interface, filling voids and grain boundary gaps; the diffusion rate follows Arrhenius kinetics, doubling approximately every 10-15°C increase.
- **Surface Deformation**: The applied pressure plastically deforms surface asperities (microscopic bumps), increasing the true contact area from initial point contacts to near-complete interfacial contact, which is essential for diffusion bonding.
- **No Liquid Phase**: Unlike soldering or eutectic bonding, TCB operates entirely in the solid state — no melting, no flux, no intermetallic compound formation at the interface, producing a clean metallurgical joint.
**Why Thermocompression Bonding Matters**
- **Fine-Pitch Interconnects**: TCB enables copper pillar bump pitches down to 10-40μm for advanced flip-chip packaging, far finer than mass reflow soldering (>100μm pitch), supporting the interconnect density required by advanced SoCs and HBM memory stacks.
- **High-Performance Joints**: TCB joints have bulk-like electrical resistivity and thermal conductivity since the bond is pure metal-to-metal without intermetallic layers, critical for high-current and high-thermal-dissipation applications.
- **3D Stacking**: Cu-Cu thermocompression bonding is the leading interconnect technology for die-to-die and die-to-wafer 3D integration, enabling vertical connections in chiplet architectures and HBM memory stacks.
- **Wire Bonding**: Gold ball bonding and wedge bonding — the most widely used chip interconnect methods — are thermocompression processes where a gold or copper wire is bonded to a pad using heat and ultrasonic energy (thermosonic variant).
**TCB Process Parameters**
- **Temperature**: 150-400°C depending on metal system — Au-Au bonds at 150-300°C, Cu-Cu requires 200-400°C due to native oxide.
- **Pressure**: 10-100 MPa applied through a bond head with precise force control — too little pressure leaves voids, too much damages underlying structures.
- **Time**: 1-30 seconds per bond — longer times improve diffusion but reduce throughput; production TCB targets < 5 seconds per die.
- **Surface Preparation**: Critical for Cu-Cu bonding — native copper oxide must be removed by plasma cleaning, forming gas (N₂/H₂), or in-situ reduction immediately before bonding.
- **Atmosphere**: Nitrogen or forming gas (N₂ + 2-5% H₂) to prevent re-oxidation during bonding, especially critical for copper surfaces.
| Parameter | Au-Au TCB | Cu-Cu TCB | Impact |
|-----------|----------|----------|--------|
| Temperature | 150-300°C | 200-400°C | Diffusion rate |
| Pressure | 10-50 MPa | 30-100 MPa | Contact area |
| Time | 1-10 sec | 5-30 sec | Bond completion |
| Surface Prep | Minimal | Oxide removal critical | Bond quality |
| Atmosphere | Air/N₂ | N₂/H₂ required | Oxidation prevention |
| Pitch Capability | 20μm+ | 10μm+ | Interconnect density |
**Thermocompression bonding is the precision solid-state joining technology for advanced semiconductor packaging** — using controlled heat and pressure to drive atomic interdiffusion between metal surfaces, creating bulk-quality metallurgical bonds that enable the fine-pitch, high-performance interconnects required for flip-chip packaging, 3D integration, and next-generation chiplet architectures.