timing closure

Static timing analysis (STA) is the method that verifies a digital chip will run at its target clock frequency by checking that every signal path meets its timing requirements — without ever simulating the circuit with input vectors. Rather than exercising the design dynamically, STA computes the worst-case propagation delay along every register-to-register path from a static delay model and confirms each path's data arrives within the window the clock allows. It is the signoff check that a design has 'closed timing,' performed by tools such as Synopsys PrimeTime, Cadence Tempus, and the open-source OpenSTA.\n\n**It checks two constraints on every path: setup and hold.** A synchronous path launches data from one flip-flop on a clock edge and must capture it at the next flip-flop on the following edge. The setup check requires the data to arrive before the capture edge by at least the setup time — this bounds the maximum delay and therefore sets the fastest the clock can run. The hold check requires the data to stay stable for the hold time after the edge — this bounds the minimum delay and guards against a fast path racing through and corrupting the captured value. Every path must satisfy both; setup violations are fixed by speeding up logic or relaxing the clock, hold violations by inserting delay.\n\n**Slack is the currency, and the worst path sets the frequency.** For each path STA computes slack = required arrival time − actual arrival time. Positive slack means the path meets timing with margin to spare; negative slack means it fails. The most negative value across the whole design — worst negative slack (WNS) — together with the sum of all violations — total negative slack (TNS) — are the numbers engineers drive toward zero during timing closure. The path with the least slack is the critical path, the bottleneck that caps the achievable clock frequency. Because STA is exhaustive and vectorless, it covers every path simultaneously, unlike simulation, which only checks the specific stimulus you supply.\n\n| Term | Meaning | Role |\n|---|---|---|\n| Setup check | data stable before capture edge | max-delay, caps clock speed |\n| Hold check | data stable after the edge | min-delay, guards fast paths |\n| Slack | required − actual arrival | margin (+ pass / − fail) |\n| WNS / TNS | worst / total negative slack | timing-closure targets |\n| Critical path | least-slack path | frequency bottleneck |\n| PVT corners | process / voltage / temp cases | multi-corner signoff |\n\n```svg\n\n```\n\n**STA runs across corners and modes, and drives timing closure.** Delay depends on process, voltage, and temperature (PVT), so signoff repeats the analysis across multiple corners — slow corners stress setup while fast corners stress hold — and across operating modes, a scheme called multi-corner multi-mode (MCMM). On-chip variation and clock uncertainty are derated in for margin. When STA reports violations, timing closure is the iterative loop that fixes them: resizing cells, buffering long nets, restructuring logic, adjusting placement, or tightening and loosening constraints, sometimes iterating all the way back to synthesis or the RTL. Sign-off STA uses parasitics extracted from the real layout, so it is the authoritative word on whether the manufactured silicon will meet frequency.\n\nRead static timing analysis through a quant lens rather than a 'check the timing' lens: it collapses the entire question of whether a chip runs at speed into a single distribution of slacks over every register-to-register path, and closure is the job of pushing the minimum of that distribution (WNS) up to zero. Setup binds the maximum delay and hold binds the minimum, so each path lives inside a window whose width is the clock period minus fixed overhead; widen the logic and you eat the setup margin, add too little delay and you break hold. Everything upstream — synthesis constraints, placement, buffering, sizing — is ultimately spending effort to shift that slack distribution to the right until nothing is left of zero.