timing closure methodology
**Timing Closure** is the **iterative process of modifying a chip's physical implementation until all timing constraints — setup, hold, max transition, max capacitance — are satisfied across all PVT corners, modes, and signoff scenarios**. Typically the most time-consuming phase and critical-path determinant of tapeout schedule.
**Setup and Hold**: Setup violation — data arrives too late (path delay + skew exceeds clock period minus setup time). Fix: upsize cells, restructure logic, add pipeline stages. Hold violation — data arrives too early. Fix: insert delay buffers, lengthen routes.
**Multi-Corner Multi-Mode (MCMM)**: Must meet timing across 30-100+ scenarios:
| Corner | Temperature | Voltage | Checks |
|--------|------------|---------|--------|
| SS/0.675V/125C | Hot | Low | Setup |
| FF/0.825V/-40C | Cold | High | Hold |
| TT/0.75V/25C | Nominal | Nominal | Reference |
| SS_aging | Aged | Low | Setup with NBTI/HCI |
Plus: operating modes (high-perf, low-power, test), OCV derating, IR drop derating.
**Closure Flow**: Synthesis (estimated wire loads) -> Placement + IPO -> CTS (actual clock latencies) -> Post-CTS optimization (setup + hold with real clocks) -> Routing -> Post-route optimization (extracted parasitics) -> Signoff STA (PrimeTime/Tempus with AOCV, SI, IR drop) -> ECO iterations.
**Common Challenges**: **Congestion-timing tradeoff** (dense placement helps timing but causes routing detours); **useful skew** (intentional clock imbalance helps setup but risks hold); **IR drop derating** (5-15% margin loss); **AOCV/POCV** (path-depth-dependent pessimism); **SI crosstalk** (10-30% added to critical paths).
**Timing closure requires holistic understanding of logic, clock distribution, power delivery, signal integrity, and process variation — the most complex and skill-dependent activity in chip design.**