transition fault

**Transition Fault** is a **simplified delay fault model that captures the inability of a gate to switch fast enough** — testing whether each node in the circuit can make both a rising (slow-to-rise, STR) and falling (slow-to-fall, STF) transition within one clock cycle. **What Is a Transition Fault?** - **Model**: 2 faults per node. STR (can't rise in time) and STF (can't fall in time). - **Test**: Two-pattern test. Pattern $V_1$ sets the initial value. Pattern $V_2$ (applied at speed) flips the value. Check if the output changes in time. - **Coverage**: Easier to achieve high coverage than path delay faults because it's gate-level, not path-level. **Why It Matters** - **Practical At-Speed Testing**: The standard model used for production at-speed test generation. - **Defect Coverage**: Catches weak transistors, resistive interconnects, and process marginalities. - **Industry Standard**: Transition fault coverage is a key metric reported by ATPG tools (Synopsys TetraMAX, Cadence Modus). **Transition Fault** is **the speed check for every gate** — ensuring each logic element can switch fast enough to meet the chip's timing requirements.