triple-well technology

**Triple-Well Technology** is a **CMOS process option that adds a Deep N-Well (DNW) beneath the standard P-well** — creating an electrically isolated P-well "tub" that can be independently biased, providing superior noise isolation and enabling body biasing for performance/power tuning. **What Is Triple-Well?** - **Standard Twin-Well**: N-well in P-substrate. P-well shares the substrate (all connected). - **Triple-Well**: Deep N-Well surrounds the P-well bottom and sides, isolating it from the substrate. - **Result**: The isolated P-well becomes a "quiet zone" for sensitive NMOS circuits. **Why It Matters** - **Noise Isolation**: Isolated NMOS transistors are shielded from substrate noise injected by neighboring digital blocks. - **Body Biasing**: The isolated P-well can be reverse-biased to reduce leakage (Forward Body Bias for speed, Reverse for low power). - **Latchup**: Significantly reduces latchup susceptibility by decoupling the parasitic bipolar paths. **Triple-Well Technology** is **acoustic insulation for transistors** — giving sensitive circuits their own private, quiet patch of silicon.