TSMC-N3

TSMC N3 is the FinFET platform that followed N5 in TSMC's roadmap, and it is the clearest example inside TSMC's own lineup of why a node name is a company-specific platform rather than a physical dimension. At a high level, how N3 moved from definition to shipping product looks like this:

A few things are worth knowing about why N3 is a distinct platform from N5, even though both are still built on the FinFET gate:

N3 kept the FinFET gate while pushing lithography and density further than N5. TSMC reports that N3 entered volume production in 2022, two years after N5, and the first major shipping products on the node were Apple's A17 Pro and the M3 family. N3's own family of enhancements — N3E and N3P — are improvements layered on the original N3 base, not a second foundation, which means a design qualified against N3E cannot automatically inherit every characteristic measured on first-generation N3 silicon.

N3's economics carry the same leading-edge weight as every node before it. Design and mask nonrecurring expense at N3 can reach hundreds of millions of dollars for a single large chip, and TSMC's own fab investment to bring N3 online ran into the tens of billions of dollars. As a pure-play foundry, TSMC builds N3 wafers for fabless customers — Apple and AMD among the earliest adopters — while TSMC itself supplies the qualified process, EUV capacity, and packaging. That cost structure is also why N3 adoption concentrates among the highest-volume, highest-margin products first, while most of the industry's wafer volume continues to run on far older, fully amortized nodes.

A marketing-node comparison across foundries is unreliable without circuit data, and N3 is the clearest internal proof. Samsung's own "3nm" platform switched to a gate-all-around transistor at roughly the same calendar window N3 shipped, while TSMC kept the FinFET gate on N3 — two different device architectures carrying a similar-sounding node digit. Density, voltage behavior, and SRAM scaling on N3 depend on the specific cell library and block implementation used, not the three-digit name alone, so any claim about N3 performance or density needs the exact TSMC variant (N3, N3E, or N3P) stated alongside it.

Packaging and system integration decide what N3's density is actually worth. CoWoS, InFO, and SoIC are TSMC's packaging families used alongside N3 dies in AI accelerators and chiplet systems, and packaging capacity has repeatedly constrained how many N3-based products could ship even when wafer capacity was available. A credible evaluation of an N3 product has to account for that packaging step, the die's yield at its reticle size, and its thermal budget — the node name on the datasheet is only the starting point.

Read TSMC N3 through a *named-platform-and-date* lens rather than a *nanometer* lens: what actually locates N3 in TSMC's roadmap is its own reported 2022 volume-production milestone and its own family of enhancements, not the digit "3" it happens to share with Samsung's differently built gate-all-around platform. N3's place between N5 and N2 is the same underlying fact as N5's pitch mismatch with other vendors: a TSMC process node is that company's platform, not a ruler the rest of the industry shares.