TSV Density

TSV density — how many through-silicon vias can be packed into a given area — is set not by lithography but by mechanics. A copper-filled via in silicon is a thermal-expansion mismatch embedded in the substrate, and the stress field it projects into the surrounding silicon shifts transistor behaviour. The exclusion region that results, not the via itself, determines the usable pitch.

Aspect ratio and fill

A TSV is characterised by its aspect ratio,

Package-level TSVs through a 50 to 100 μm interposer run 5 to 10 μm wide at aspect ratios of 10:1 to 20:1. Nano-TSVs used in backside power delivery are a few hundred nanometres across, through a few hundred nanometres of remaining silicon, at aspect ratios near 10:1. Both are hard to fill for the same reason: transport into a deep feature is conductance-limited, so plating additives and deposition chemistry must be tuned to deposit from the bottom up rather than pinching the opening shut. A seam or void left in the fill becomes a stress concentrator and a reliability failure.

The via's electrical contribution is straightforward and unforgiving:

Resistance rises as the inverse square of diameter, so density and conductance pull in opposite directions. The capacitance to substrate adds an RC penalty that matters for signal TSVs and is largely irrelevant for power ones, which is why signal and power vias are often sized differently on the same die.

Thermo-mechanical stress and the keep-out zone

Copper expands at roughly 17 ppm/K, silicon at 2.6. Cooling from the plating and anneal temperature therefore leaves the copper in tension and the surrounding silicon under a radial stress field that decays as the inverse square of distance from the via axis:

with $a$ the via radius. That stress is not merely a fracture concern — it changes the silicon's band structure. Through the piezoresistive effect, carrier mobility shifts in proportion to the local stress,

so a transistor placed too close to a TSV has a different drive current from an identical transistor placed far away, and the shift is anisotropic in the crystal. Since the piezoresistive coefficients differ in sign and magnitude between electrons and holes, the same stress field detunes NMOS and PMOS by different amounts, breaking the matching that analogue and timing-critical circuits depend on.

The keep-out zone is the radius inside which that shift exceeds what the design can tolerate. Because stress falls as $1/r^{2}$ while the tolerable shift is a fixed percentage, the KOZ radius scales roughly linearly with via radius — typically 3 to 10 μm around a package-level TSV. The area cost is quadratic:

and it is why TSV arrays are placed in dedicated regions rather than scattered through active logic.

Pitch scaling strategies

Three levers reduce the density penalty. Shrinking the via shrinks the stress field with it, since the KOZ scales with via radius — this is precisely why nano-TSVs for backside power carry a nearly negligible keep-out penalty while interposer TSVs carry a large one. Replacing solid copper with an annular fill or a lower-expansion metal reduces $\Delta\alpha$ and therefore the projected stress directly. And placing vias in regular arrays lets the overlapping stress fields be characterised once and modelled as a known offset, rather than being treated as worst-case around each isolated via.

What actually binds

For interposer TSVs the limit is mechanical: the keep-out zone dominates and the via count is bounded by area a designer is willing to sterilise. For nano-TSVs in backside power delivery the keep-out penalty largely vanishes with the scale, and the binding constraint moves to resistance, since $R \propto 1/d^{2}$ punishes the shrink that made the KOZ negligible. The two regimes are limited by opposite physics, which is why they are engineered by different teams with different figures of merit.