keep-out zone
**Keep-Out Zone (KOZ)** is the **exclusion region around a through-silicon via where no active transistors or sensitive circuits may be placed** — defined by the distance from the TSV center beyond which TSV-induced thermo-mechanical stress drops below the threshold that would cause unacceptable transistor performance variation, typically 2-10 μm radius depending on TSV diameter, technology node, and performance tolerance.
**What Is a Keep-Out Zone?**
- **Definition**: A design rule that prohibits placement of active devices (transistors, diodes) within a specified distance of a TSV center, ensuring that TSV-induced stress does not cause threshold voltage shifts, mobility changes, or matching degradation that would violate circuit specifications.
- **Stress-Driven**: The KOZ boundary is set where the TSV-induced stress field decays to a level that causes < 1% transistor performance variation — this threshold depends on the circuit's sensitivity to performance variation (analog circuits need larger KOZ than digital).
- **Area Penalty**: Each TSV with its KOZ consumes silicon area that cannot contain transistors — for a 5 μm diameter TSV with 5 μm KOZ radius, the exclusion area is π × (5 μm)² ≈ 78 μm², which becomes significant when thousands of TSVs are needed.
- **Design Rule**: KOZ is specified in the process design kit (PDK) as a minimum spacing rule between TSV edges and active device regions — EDA tools enforce this rule during place-and-route.
**Why Keep-Out Zones Matter**
- **Performance Predictability**: Without KOZ, transistors near TSVs would have unpredictable performance due to stress-induced mobility and Vt shifts — KOZ ensures all transistors operate within their specified performance envelope.
- **Matching**: Analog circuits (current mirrors, differential pairs, ADCs) require precise transistor matching — TSV stress creates systematic mismatch that degrades analog performance, requiring larger KOZ for analog blocks.
- **Area Efficiency**: KOZ directly reduces the usable silicon area for transistors — a 3D IC with 10,000 TSVs at 10 μm KOZ radius loses ~3.14 mm² of active area, potentially 5-10% of a small die.
- **Design Complexity**: KOZ constraints complicate place-and-route because TSV locations must be co-optimized with transistor placement — TSVs placed in the wrong location can create KOZ conflicts that require design iteration.
**KOZ Sizing Factors**
- **TSV Diameter**: Larger TSVs generate more stress and require larger KOZ — a 10 μm TSV needs ~2× the KOZ of a 5 μm TSV.
- **Technology Node**: Advanced nodes with smaller transistors are more sensitive to stress — 5 nm FinFETs may require larger KOZ than 28 nm planar transistors for the same TSV.
- **Circuit Type**: Digital logic tolerates ±5% performance variation (small KOZ), while precision analog requires < ±0.1% matching (large KOZ).
- **Liner Compliance**: Polymer liners that absorb stress reduce the KOZ by 30-50% compared to rigid SiO₂ liners.
- **Temperature Range**: Wider operating temperature range increases peak stress and requires larger KOZ — automotive (-40 to 150°C) needs larger KOZ than consumer (0 to 85°C).
| Circuit Type | KOZ Radius (5 μm TSV) | KOZ Radius (10 μm TSV) | Tolerance |
|-------------|----------------------|----------------------|-----------|
| Digital Logic | 2-3 μm | 4-6 μm | ±5% Vt |
| SRAM | 3-5 μm | 6-10 μm | ±3% Vt |
| Analog (moderate) | 5-8 μm | 10-15 μm | ±1% matching |
| Analog (precision) | 8-15 μm | 15-25 μm | ±0.1% matching |
| I/O Drivers | 1-2 μm | 2-4 μm | ±10% (tolerant) |
**The keep-out zone is the design-level cost of 3D integration** — trading silicon area around each TSV for guaranteed transistor performance predictability, with KOZ minimization through smaller TSVs, compliant liners, and stress-aware design tools being essential for maximizing the density benefits of 3D stacking.