UCIe Interconnect Standard

# UCIe — Universal Chiplet Interconnect Express

Chiplet packages only work as a real ecosystem if dies from different vendors can actually talk to each other across the same package, and before 2022 every company building chiplets wired that connection its own proprietary way. UCIe (Universal Chiplet Interconnect Express) is the open industry standard built to end that fragmentation — a published specification defining the physical layer, protocol, and software stack for die-to-die communication, so a chiplet designed by one company can connect to a chiplet from another without custom interface engineering on either side.

UCIe defines two distinct physical-layer tiers because a chiplet connected across a cheap organic substrate faces a completely different interconnect problem than one sitting on a silicon interposer. The standard-package UCIe PHY targets longer reach and coarser bump pitch, suited to chiplets mounted directly on an organic package substrate without an interposer — lower bandwidth density, but compatible with cheaper, more widely available packaging infrastructure. The advanced-package UCIe PHY targets the much finer bump pitches achievable on a silicon interposer or through hybrid bonding, delivering dramatically higher bandwidth density per millimeter of die edge at the cost of needing that more expensive advanced-packaging infrastructure in the first place. A chiplet vendor picks the tier that matches its target package, and both tiers speak the same protocol stack above the physical layer.

UCIe sits explicitly at the die-to-die level, deliberately layered to reuse PCIe and CXL above it rather than reinventing the whole protocol stack from scratch. Above the physical layer, UCIe's protocol stack maps directly onto existing PCIe and CXL transaction semantics, so software and higher-level IP that already understands PCIe or CXL can run over a UCIe die-to-die link largely unmodified — a chiplet can expose what looks, from the protocol's perspective, like a PCIe or CXL device sitting one hop away instead of across a board-level connector. That reuse is a deliberate design choice: it lets the standard focus its real engineering effort on the hard part — the physical layer and the die-to-die adapter layer that's genuinely new — instead of also having to invent and gain industry adoption for an entirely new transaction protocol.

The consortium behind UCIe spans the companies that actually have to agree for a chiplet ecosystem to function at all, which is exactly the coordination problem the standard exists to solve. Intel, AMD, Arm, Qualcomm, Samsung, TSMC, and Google were among the founding members of the UCIe Consortium when the specification first published, later joined by Microsoft, Meta, and others — a deliberately broad coalition spanning chip designers, foundries, and the hyperscalers who are themselves increasingly designing custom silicon. That breadth matters specifically because UCIe only delivers value once multiple independent companies' chiplets can interoperate in the same package; a standard backed by only one company would just be a proprietary interface with a different name.

Reflow solder bump and underfill, covered earlier in this walkthrough, handle the mechanical and electrical joint for any flip-chip connection generally. UCIe defines what happens at a higher layer above that physical joint specifically for chiplet-to-chiplet communication — the protocol and electrical signaling standard that turns a set of mechanically connected dies into an actual interoperable multi-vendor system, which is the piece the rest of advanced packaging's mechanical engineering exists to make possible in the first place.