what is a pdk
A PDK, or process design kit, is the file package a foundry hands its customers so their chip designs actually work on that foundry's silicon: transistor models, standard-cell libraries, design rules, and verification decks, all calibrated to one specific manufacturing process. Without it, a design team has no way to predict how their circuit will behave once it is actually built in silicon, and no way to check that their layout even obeys the physical rules the fab's lithography and etch tools can print.
```flowchart
{
"rows": [
{ "type": "nodes", "items": [
{ "title": "Foundry qualifies a process", "sub": "node, transistor type, metal stack", "tone": "neutral" }
]},
{ "type": "arrow" },
{ "type": "group", "title": "PDK release", "note": "delivered under NDA to design partners", "items": [
{ "title": "Device models", "sub": "SPICE, transistor behavior", "tone": "green" },
{ "title": "Standard-cell library", "sub": "logic gates, flip-flops", "tone": "green" },
{ "title": "Design rules", "sub": "DRC deck, spacing, width limits", "tone": "green" },
{ "title": "Verification decks", "sub": "DRC, LVS, parasitic extraction", "tone": "green" }
]},
{ "type": "arrow" },
{ "type": "nodes", "items": [
{ "title": "Design team builds chip", "sub": "RTL through GDSII", "tone": "orange" },
{ "title": "Tapeout to that foundry", "sub": "only valid for this PDK", "tone": "orange" }
]}
]
}
```
**A PDK is what makes "the same design" actually mean something different at every foundry.** The transistor models inside it describe exactly how that foundry's specific process turns on, switches, and leaks at a given voltage and temperature, so a circuit simulated against TSMC's PDK behaves differently in simulation than the identical circuit simulated against Samsung's or GlobalFoundries' PDK, even at a nominally similar node. A chip cannot be designed in the abstract and then handed to any fab; it is designed against one PDK from the start.
```svg
```
**Standard-cell libraries inside the PDK save design teams from reinventing basic logic from scratch.** Rather than hand-laying out every AND gate and flip-flop, designers pull pre-characterized cells straight from the library, already validated for timing, power, and area on that specific process. The richness of this library — how many drive strengths, how many specialty cells, how well it is documented — is a real, if less visible, measure of how mature a foundry's ecosystem actually is.
**The design-rule deck is the PDK's connection back to lithography and etch.** Every minimum line width, spacing, and via size in that deck exists because the fab's scanners and etch tools have a physical limit on what they can reliably print and transfer at that node, so a layout that violates the rule deck is a layout the fab genuinely cannot manufacture with acceptable yield — it is not a formality, it is the physics of the process expressed as design constraints.
**PDK maturity is one of the biggest hidden costs in a foundry decision.** A cheaper node with a thin, immature PDK and sparse third-party IP support can cost a design team more engineering months than a slightly pricier node backed by a deep, well-documented kit and a wide library of pre-qualified building blocks — which is exactly why PDK quality belongs on the same shortlist as price and process node when comparing foundries.
| PDK component | What it contains | Why it matters |
|---|---|---|
| Device models | SPICE-level transistor behavior | Determines whether simulation matches real silicon |
| Standard-cell library | Pre-built logic gates, flip-flops | Saves months of manual cell design |
| Design rules (DRC) | Minimum widths, spacing, via rules | Encodes what lithography and etch can physically print |
| Verification decks | DRC, LVS, parasitic extraction | Confirms the layout is manufacturable before tapeout |
Read a PDK through a translation lens: it is the dictionary that turns an abstract circuit idea into instructions one specific fab's lithography, etch, and deposition tools can actually execute, and every constraint inside it — a cell's timing number, a minimum spacing rule, a model's leakage curve — is a fact about that foundry's physical process, restated in a form a design tool can check before a single wafer is committed to production.